Digital power solutions whip efficiency into shape

Digital power solutions whip efficiency into shape

Digital controllers offer big advantages over traditional solutions, targeting consumer to super-computer applications

BY CARL SMITH, Marketing Director,
International Rectifier
www.irf.com

Next-generation systems demand the highest power conversion efficiency in support of leading-edge CPU and GPU designs for servers, motherboards, and graphics cards, all while system form factors are shrinking, steady-state and dynamic load power needs become ever more challenging, and design cycles reduce. Digital solutions offer true built-in capabilities to maximize efficiency across the entire operating range of the load on a real-time basis, surpassing the capability of conventional analog solutions.

So, first of all, what value does digital bring to power design?

The emergence of digital power semiconductor technology has certainly raised the question of value over and above traditional solutions. Purist power designers are comfortable using traditional analog solutions and may be hesitant to attempt solving power design challenges in the digital domain. Analog solutions are falling short in providing all that is needed to power next-generation processors, including ease of design, flexibility, on-the-fly performance optimization, density, component count reduction, transient performance, diagnostics, and efficiency …. and the list goes on.

Next-generation processors require more than just high efficiency under static load power conditions; they demand smart power processing, with dynamic optimization on-the-fly that boosts performance across the entire operating range of the processor. Digital PWM controllers offer tremendous benefits over analog solutions, while being very user friendly.

The value of digital

There are several key areas of value when considering digital PWM controllers versus traditional analog solutions. Firstly, loop compensation and programming of operating conditions and fault protection modes are typically configured with external R’s and C’s “shrubbery” components surrounding the analog controller as it has minimal, if any, ability to take care of this in the controller itself — while increasing overall solution size.

Any fine tuning or change of settings for these parameters requires a change of on-board hardware with different component values which can make the entire design cycle more complicated and time consuming. Optimizing loop compensation in a digital controller is extremely easy to accomplish, it is built into the controller, requires zero external components and any necessary fine tuning for peak performance is software controlled.

Programmable fault protection thresholds and configuration of operating conditions are also all built into the digital controller and the information is stored in memory, and again, requires zero external components. These settings can also be re-configured easily via software and allows for extremely flexible system design. Analog controllers are limited in telemetry options, providing typically only current and temperature information with limited I2 C capability, whereas digital solutions offer a more comprehensive range of telemetry options via I2 C, including current, voltage, temperature, and power providing full 24 x 7 monitoring of the load in the system.

Two of the most significant advantages of digital controllers are the ability to dynamically adjust in-circuit performance to maximize efficiency and reduce power losses across the entire operating range of the processor, while at the same time meet the extremely challenging transient requirements, as the processor rapidly moves from full-load to sleep states and back again, minimizing overall bill-of-materials component count and system costs. International Rectifier’s latest versatile family of CHiL digital PWM controllers offer proprietary efficiency shaping technology including dynamic phase control (DPC) and variable gate drive (VGD) while also offering an adaptive transient algorithm (ATA) to whip efficiency into shape!

Efficiency shaping technology

The challenge from one system generation to the next is always to find that extra level of performance in terms of electrical efficiency, to squeeze more power into a smaller area and to stay within challenging dissipation-density limits to keep thermals stable and ensure reliable operation. The initial focus tends to be on maximizing efficiency as this directly impacts power dissipation and temperature rise in the system.

Traditional solutions only allow for optimization of efficiency for one key-performance metric, and there are then unfortunately trade-offs in performance to consider once operating conditions change. For instance, a design optimized for best thermal design current (TDC) or full-load performance may have a negative trade-off at light loads and/or peak efficiency and vice versa. IR’s range of CHiL digital PWM controllers offer an easy-to-use efficiency shaping technology that allows maximizing light-load and peak efficiency without a negative impact in TDC efficiency (see Fig. 1 ).

Fig. 1: Efficiency optimization trade-offs.

When operating at high-current TDC load conditions, conduction losses will dominate in each phase, so ideally the multi-phase voltage regulator should be operating with all phases on to maintain a practical current-per-phase target and the MOSFETs in the power stage should be driven with as high of a gate-drive voltage as possible to minimize on-state resistance (RDS(on) ). Conduction losses are mainly a function of iTDC 2 x RDS(on) in the MOSFETs so minimizing current-per-phase with high phase count and over-driving the gate voltage for the MOSFETs enables the best TDC efficiency.

When operating at light load conditions or when optimizing for peak efficiency, MOSFET switching losses typically dictate performance. Reducing phase count by phase shedding is one way to help boost light-load performance. In addition, the gate drive voltage (VGS ) for the MOSFETs should be reduced, as it has a direct impact on switching losses in the MOSFETs as a function of VIN x Qsw x Fsw , where Qsw is post-gate threshold switching charge that is minimized with lower gate drive voltage as well as in the gate driver IC as a function of QG x VGS x Fsw (see Fig. 2 ).

Switching losses can also be minimized with lower switching frequency. This can be kept at practical levels while also meeting aggressive transient requirements when using the adaptive transient algorithm (ATA) to increase switching frequency only when you need to, during step-up load transients, and return to a lower steady state switching frequency during static load conditions.

Fig. 2: IR Efficiency shaping technology.(dynamic phase control and variable gate drive)

The digital PWM controller scales phase count automatically, adding and shedding phases as load conditions vary via a per-phase programmable threshold that is programmed into the controller. The thresholds can be tuned to give the best efficiency across the entire load range of the processor. Loop coefficients are automatically scaled to ensure stable operation.

The variable gate drive (VGD) feature dynamically adjusts gate drive voltage to the MOSFETs depending on per-phase load conditions. The user can program the minimum gate drive voltage and slope versus load current via the programmed configuration file in the digital PWM controller to optimize performance (see Fig. 3 ).

Fig. 3: Variable gate drive.

Adaptive transient algorithm

In traditional analog based designs, transients are dealt with at the same switching frequency as static load conditions. This creates a design trade off problem for the power system designer. To improve efficiency, the designer would prefer to keep switching frequency low, but then this means more output capacitance is required to support transient conditions, within spec, versus a system designed with higher frequency.

More capacitance means increased bill-of-materials costs and larger board area is required to support transient load conditions. On the other hand, increasing switching frequency allows for less capacitors and smaller inductors that will reduce overall size and costs while meeting transients, but the trade-off is a hit in efficiency.

IR’s adaptive transient algorithm provides the best of both worlds. The ATA is a proprietary hybrid pulse-width modulated (PWM) and pulse-frequency modulated (PFM) scheme that operates at a normal switching period during static load conditions, and only moves to a lower switching period (higher switching frequency), with fixed on-time to balance phase currents and help prevent inductor saturation, when required to support fast load changes (step-up) (see Fig. 4 ).

This also allows for reduced capacitor count, reducing solution size and cost. Also, for load release events, pulses can be skipped in order to increase the switching period (reduce switching frequency) to help limit the amount of output voltage overshoot.

Fig. 4: Adaptive transient algorithm.

Digital controller technology sets standard

Digital controllers offer significant advantages over traditional solutions, and are being adopted in a wide variety of market segments from consumer to super-computer. IR’s versatile range of CHiL digital PWM controllers can be combined with PowIRstage solutions to enable high-performance, high-density, complete end-to-end voltage regulator solutions that can be easily tailored to meet the power delivery requirements of next-generation processors and DDR memory applications. ■