Using CMOS and BiCMOS Logic Devices

As general purpose components, logic devices are used at different frequencies and power supply voltages in many different varieties of applications. This large diversity has produced the need to express a single parameter that can be used in determining the power dissipation of a device in a given application. This application note describes different components of power dissipation and how they may be calculated.

1. Static Considerations

CMOS
When a CMOS device is not switching and the input levels are GND or VCC, the p-channel and n-channel transistors do not conduct at the same time; no direct MOS transistor channel path exists between VCC & GND. In practice however, thermally generated minority carriers, which are present in all reverse biased diode junctions, allow a very small leakage current to flow between VCC and GND. As this leakage current is typically a few nA, quiescent CMOS power dissipation is extremely low. Maximum quiescent power dissipation for the above conditions is calculated as:

                                                                          (1)

     Where:

          Icc is specified in the device datasheet.

BiCMOS
In the case of BiCMOS devices; the current in the output bipolar stage is different when the output is set high or low. This results in two datasheet specifications for quiescent current & . Quiescent power dissipation for input levels of GND or Vcc is calculated as:

                                                                          (2)

     Where:

           n1 is the number of outputs LOW

           n2 is the number of outputs HIGH

Input stage current due to GND
In the case where the input levels of the device are not held at GND or VCC, a direct MOS transistor current path can exist between VCC and GND; this leads to additional supply current through the input buffer stage of both CMOS and BiCMOS devices, and additional power dissipation. In device datasheets this is represented as ∆ICC, the additional current due to an input level other than VCC or GND. In the case of 5.5 V logic families this parameter is generally measured at an input voltage of VCC – 2.1; in the case of 3.3 V logic families it's measured at an input voltage of VCC – 0.6 V. Static power dissipation is then calculated as:

                                                                          (3)

     Where:

          n is the number of inputs at the intermediate level.

2. Dynamic Considerations
When a device is clocked, power is dissipated through the charging and discharging of on-chip parasitic and load capacitances. Power is also dissipated at the moment the output switches when both the p-channel and the n-channel transistors are partially conducting. This transient energy loss is typically only 10% of that due to parasitic capacitance.

The total dynamic power dissipation per device is:

                                                                         (4)

     Where:

          CPD is the power dissipation capacitance per buffer
          fi is the input frequency
          fo is the output frequency
          CL is the total external load capacitance per output

It should be noted from the Equation (4), that CPD is a useful parameter for determining power dissipation in any device for which power dissipation is a linear function of frequency. Figure 1 shows ICC as a function of frequency for the devices listed in Table 1. From this we can conclude that for all of NXP's CMOS and BiCMOS logic families CPD can be used in order to determine the worst case power consumption of a device in a given application.