At the recent Linley Processor Conference, Imagination Technology (now including MIPS) introduced the MIPS P5600 core IP that is said to provide industry-leading 32-bit performance together with class-leading low power in a silicon footprint up to 30% smaller than comparable CPU cores. The IP features 128-bit SIMD, hardware virtualization, and Extended Physical Addressing (XPA) that allows a 32-bit system to access physical memory up to 1 Terabyte (40-bits).
The processor has 256 system interrupts, a 16-stage pipeline, and 128 bit CM busses. The MIPS architecture core will be available for licensing in Q4 2013 and performance is said to exceed 5 CoreMark/MHz and 3.5 DMIPS/MHz. The IP will operate at 1 to 2 GHz on the TSMC 28HPM process.
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