Digital video interface protocols

Serial video interface protocols enable a cost-effective method of connecting video devices together. HDMI and DisplayPort interfaces are the most common video bridges to the video displays in consumer devices such as set-top boxes, DVD players, gaming consoles, and various types of computers.

Digital video interface protocols can be categorized into two groups: device to device or external interface, and internal chip-to-chip interfaces. The most popular interfaces for external use are DVI, HDMI and Displayport. Internal interfaces include embedded DisplayPort (eDP), V by One HS, LVDS (Low Voltage Differential Signaling) for display panels and MiPi (Mobile Industry Processor Interface) for smartphones and tablets.

DVI and HDMI use the same electrical format, called transition-minimized differential signaling (TMDS). TMDS incorporates a coding algorithm that can help reduce electromagnetic interference over an extended length of copper cable. It converts the original 8-bit video into a 10-bit code using an 8b10b scheme. This code creates a sequence that minimizes the 0-1 transition to reduce emissions. TMDS in DVI and HDMI use three data lanes and one clock lane. Each data lane has a maximum data rate of 3.4 Gbits/s for HDMI 1.4 and 6 Gbits/s for HDMI 2.0. The maximum clock rate is 340 and 600 MHz, respectively. Both the data and clock lanes use current mode logic (CML), dc coupled and terminated with 50 Ω to 3.3 V. Figure 1 shows the physical interface between TMDS transmitter and receiver. In additional to the main data/clock channels, there are side-band channels called Display Data channel (DDC) with extended display identification data (EDID). DDC allows the display to communicate the supported modes to the video source and EDID communicates to the source regarding resolution. The DDC is basically an I² C link between the source and the sink.

Fig. 1: The transition-minimized differential signaling (TDMS) DC-coupled interface.

A subset of the HDMI standard for mobile devices is called Mobility High-definition Link (MHL). MHL multiplexes the original three HDMI video lanes into a single 2.25-Gbit/s lane. The MHL clock is embedded in this lane using a common mode of differential data signal. MHL uses a micro-USB as the key interface at the mobile device level.

DisplayPort is a competing standard to HDMI. DisplayPort uses the same 8b10b coding scheme to reduce RF interference. The clock is embedded into the main video lanes. There are four main video links and an auxiliary (AUX) channel similar to DDC of HDMI. DisplayPort uses a low-voltage ac-coupled different signal at 400 mVp-p. The termination voltage is less than 2 V. Figure 2 shows the physical interface. The AUX channel is also AC coupled and with two modes, the default mode is 1 Mbit/s and the “Fast” mode is 720 Mbits/s. The data rate for each of the main lanes can be set to 1.62 Gbits/s (Reduced Bit Rate, RBR), 2.7 Gbits/s (High Bit Rate, HBR) or 5.4 Gbits/s (HBR2) depending on the video resolution.

Fig. 2: The DisplayPort ac-coupled interface.

There are two subsets of Displayport, Mobility DisplayPort (MyDP) and Embedded Displayport (eDP). MyDP competes with MHL in the mobile applications. eDP is an internal interface link between the video processor and the display panel. The main link is identical to the regular DisplayPort. In eDP, the AUX channel provides additional functions such as touch screen control.

MyDP also uses the micro-USB connector. MyDP multiplexes the original four main lanes into a single main lane running at the same set of data rate of 1.62, 2.7, or 5.4 Gbits/s. The AUX channel has the same default of 1 Mbit/s or the “Fast” mode of 540 Mbits/s, but singled ended.

The traditional interface between the video processor and the LCD or LED display panel is LVDS. The number of LVDS lanes increases significantly when the resolution and the panel size get larger. To reduce the number of LVDS lanes, a serial approach is used. Some of the serial interfaces include eDP, iDP, and V by One HS.