Research Triangle Park, NC – October 28, 2014: Driven by process scaling and the need for continually shrinking devices, 3D integration is poised to impact not only future semiconductor device designs, but also will provide new approaches to heterogeneous systems packaging, including for MEMS and the emerging IoT marketplace. The 11th annual 3D Architectures for Semiconductor Integration and Packaging Conference (3D ASIP), December 10-12, 2014, at the Hyatt Regency San Francisco Airport, Burlingame CA, provides industry leaders from around the world an outstanding venue for sharing the latest trends and insights in the 2.5/3D IC ecosystem. This annual event is organized by RTI International.
Steve Schulz, president and CEO of Si2, who will deliver one of the keynote addresses, A Design Ecosystem for Internet of Things, How 3D IC Standards will Enable a New Growth Paradigm states that “although 3D integrated circuits (3DICs) have long been anticipated as the major emerging alternative to classical process scaling, the coming wave of devices driving the Internet of Things (IoT) era will mandate a new set of integration requirements that only 3DICs can properly satisfy.” He continues, “the need to integrate a wide range of functionality – spanning digital, memory, analog, RF, MEMS, sensors, and energy harvesters – cannot be economically addressed exclusively with single-die solutions.”
The keynote session will feature two additional speakers. Robert Sturgill, director of Hybrid Memory Cube Solutions Micron Technology, will discuss advanced 2.5/3D memory solutions, and Xin Wu, vice president of Silicon Technology for Xilinx, will focus on Xilinx’ 3D approaches and ultrascale 3D FPGA capability.
Conference sessions include IoT, Memory and More than Moore, Perspectives on Manufacturing and Cost, Design Analysis and Modeling, The World in 2.5D, Interposers, Monolithic 3D Integration, 2.5/3D Systems – Bringing It All Together.
A complete list of presenting companies is available on the conference website.
This year’s conference features an expanded full-day pre-conference symposium on design and manufacturing for practical 2.5D and 3D implementation. The morning session, 2.5/3D-IC Design Tools and Flows , has been organized by eda2asic President Herb. Reiter. The afternoon session, 3D Integration: 3D Process Technology , organized and moderated by Phil Garrou, IEEE Fellow and Consultant, takes a quick look at the current status of the 3D marketplace and a detailed look at the status of the 3D TSV-based processing technology. Visit www.3dasip for detailed information on the programs and speakers.
Registration and additional information is available at: www.3dasip.org.
About 3D ASIP
3D Architectures for Semiconductor Integration and Packaging (3D ASIP) is the longest running conference series on this topic. With invited speakers and participants from leading companies and organizations around the world, the conference aims to provide information critical to planning ongoing and future business and technical efforts impacted by 2.5/3D developments and opportunities. For more information, visit www.3dasip.org.
Via: 3D ASIP
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