Xilinx demonstrated an end-to-end 400 Gbits/s Ethernet solution by Xilinx at the Ethernet Technology Summit in Santa Clara. The demo showcased the industry’s first single-chip 400G method. It uses a Virtex UltraScale VU095 device directly connected to four sets of Sumitomo Electric CFP4 LR4 fiberoptic modules. Fiber cables are connected to the Spirent Communications 400GE test set that uses four sets of Oclaro CFP2 LR4 optical modules and shows zero errors.
Mark Gustlin shows off the 400GE system at the Ethernet Technology Summit
This demo shows off the XCVU095’s four 100 Gbit/s Ethernet ports. The Ethernet blocks are compliant to IEEE Std 802.3ba and include both the 100G MAC and PCS logic with support for IEEE Std 1588v2 1-step and 2-step hardware time stamping. The FPGA has 1,129 effective logic elements, 941 logic cells, 68 Mbits of block RAM, 768 DSP slices, and four PICe blocks. The chip can have up to 780 I/Os, six 150G Interlaken ports, and 32 32-Gbit/s transceivers. UltraScale devices use 16 nm FinFET technology.
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