Selecting the optimum MOSFET for off-line switching power supplies

BY MARTY BROWN
Senior Consultant
D3 Semiconductor
www.d3semi.com

Today, the choice of silicon MOSFETs falls into two major divisions: the planar and/or trench MOSFET and the superjunction MOSFET. Planar MOSFETs have their active region close to the surface of the die (Fig. 1a ). To decrease the R_DS(on) , additional die area is required, and to increase the voltage of the MOSFET, the die must be  made thicker. In comparison, the superjunction MOSFET (Fig. 1b ) uses its die depth to increase the channel area, which significantly reduces its R_DS(on) for a given die area. By greatly increasing the conduction area within a much smaller surface area, superjunction MOSFETs allow for a smaller die size for each current rating as compared to planar MOSFETs. As an added benefit, they offer much lower parasitic capacitances with much faster switching speeds.

Fig. 1a: Standard planar MOSFET construction.

Fig. 1b: Construction of a generalized superjunction MOSFET.

Table 1 compares the key parameters between a standard planar MOSFET and a high-performance +FET superjunction MOSFET, newly introduced by D3 Semiconductor, which have nearly identical drain voltage and current ratings. As shown, the R_DS(on) and the MOSFET’s annoying parasitic capacitances are much lower with the superjunction MOSFET, and the switching speed is more than three times faster. The truly remarkable factor is that the uncapped die area of the superjunction MOSFET is one-third that of the planar MOSFET.

Table 1: Comparison of a representative standard versus a D3 superjunction MOSFET.

The efficiency comparisons between a superjunction MOSFET and standard planar MOSFET speak volumes about how a designer can improve cost and switching performance of a typical off-line switching power supply. D3 Semi’s superjunction MOSFET exhibits a more-than-73% reduction in its die area, a more-than-50% reduction in input gate capacitance (C_iss ), and a more-than-69% reduction of the value of the miller capacitance (C_rss ).

MOSFET performance in power supplies
Fig. 2 illustrates a very common plot when testing the efficiency of a switching power supply over its expected load range. The efficiency exhibits a peak at some load between the maximum and minimum loads. With a good design, that peak will be at or near where the supply operates more than 90% of its operating life. Its location and its peak value is totally determined by trading off the various MOSFET parameters during the design process.

Fig. 2: Efficiency versus load — the influences.

At light loads, the on-time (duty cycle) is small. This makes the MOSFET conduction losses much less significant. Here, the switching and gate drive losses dominate its efficiency. Within the typical power supply, the switching frequency is relatively constant, so the switching and drive losses are also relatively constant.

At higher loads, the MOSFET (and output rectifier) conduction losses become more significant than the drive and switching losses. Here, the value of R_DS(on) becomes important. As with all resistive switches, the supply’s efficiency deteriorates as the output load increases. This non-linear effect is the ID² (R_DS(on) ) loss.

Design considerations
There are many subtle aspects when considering the best MOSFET for a switching power supply design. Conventional wisdom holds that the lowest R_DS(on) yields the most efficient supply. However, looking only at a power supply’s efficiency at one operating condition can be very misleading. To get a very clear understanding of the performance of the power supply over its complete operating range, one should consider the variation in efficiency over the expected range of output load (W) and input voltage.

That peak of the efficiency, as seen in Fig. 3 , can help with selecting an “optimum” MOSFET for your design and operating range. That is where the peak efficiency occurs where your supply spends more than 90% of its operating life.

Fig. 3: Example of choosing the lowest R_DS(on) MOSFET within a supply.

Fig. 4 is a qualitative representation of the behaviors of the three losses over the load range. This only describes the losses individually and not collectively. When these losses are combined (summed), the result is much more informative.

This example shows what can happen when the designer chooses the lowest R_DS(on) MOSFET within a family of high-voltage MOSFET offerings. The result is an overall lower supply efficiency as compared to a higher R_DS(on) (smaller die area) device being selected. (Of course, there is a whole set of variations in the results, given the range of MOSFET parameters and operating conditions. This represents a worst-possible-case outcome of a poor design decision.)

Fig. 4: The behavior of the three losses over the load range.

Choosing the lowest available R_DS(on) MOSFET increases the C_iss and C_rss , which, in turn, requires a higher peak gate drive current. Because the gate driver cannot supply that peak current in the short period, the MOSFET switches slower (longer tSW and lower dVDS/dt). This drastically increases the significant drain-source switching loss and the gate driver loss. The gate driver experiences a larger loss related to the amplitude of the peak gate current and the lengthened time required to switch the MOSFET.

The resulting drive and drain-source switching loss can make the efficiency noticeably worse at the lighter loads and also arithmetically lowers the combined efficiency curve by the amount of these losses. This degrades the overall efficiency, especially at the lighter loads, and pushes the peak efficiency point toward the higher loads.

The perceived benefit of a reduced R_DS(on) does, indeed, decrease the conduction loss, but its overall effect is somewhat marginal. The conduction loss is mainly responsible for the “curviness” of the efficiency curve. The degree of curvature becomes lesser for lower R_DS(on) s. The increase in the efficiency due to the reduced R_DS(on) is only arithmetic. The conduction loss is still overwhelmingly dominated by the square of the drain current. This helps at the higher loads, where the efficiency is dominated by the conduction loss. In the case of Fig. 4 , the increase in the switching and drive losses were larger than the improvement in the raised efficiency level and the curvature. This is a very possible outcome.

For the average engineer, not really understanding the physical influences of MOSFETs, the choice of MOSFET is made once and the results are accepted. To the informed designer, this is only acceptable when the MOSFET behavior is more thoroughly examined.

There are many subtle aspects when considering the best MOSFET for a switching power supply design. A little elementary understanding of the construction of the MOSFET, as well as how its interdependent parameters affect the power supply’s performance, allow the designer to see why migrating from standard planar MOSFETs to superjunction MOSFETs is compelling.