Microchip dual-core DSC targets high-end embedded control systems

By Aalyia Shaukat, contributing writer

Microchip Technology Inc. recently released a dual-core digital signal controller (DSC) designed to simplify product development while strengthening security and increasing the ease of integration. The dsPIC33CH is a DSC with two embedded cores, each to function as a master and a slave, respectively, thereby eliminating the need for multiple DSC chips. This minimizes the system-level debugging time. The dual-core design allows for multiple teams to develop codes independently for various processes. The DSC chip will integrate all of the digital functions into one chip.  

Simple DSP implementation
The dual-core dsPIC DSC enables multi-team software development for more rapid product time to market. The slave core can execute time-critical control code while the master core is running the user interface and various systems functions. By splitting the workload between two processors, the chips can handle complicated algorithms while simultaneously running user interface software or other programming. The ability to run multiple programs simultaneously allows for a highly integrated method to manage multiple sophisticated algorithms. This is useful in many embedded applications such as drones, wireless power, server power supplies, and automotive sensors.

In a recent Mouser product brief, an example shows where system performance and overall responsiveness could be increased by using the master core to manage the power management protocol, PMBus, for system monitoring while the slave core handles the math-intensive algorithms involved. The division of labor between the processors allows for a higher power density, higher switching frequencies, and smaller component dimensions. The chip has been designed for the maximum analog integration possible with high-speed ADCs, DACs with waveform generation, and analog comparators and PGAs. This high analog integration allows for more functionality in less space, allowing for a more efficient chip all around.  

dsPIC33CH specifications
The dsPIC33CH contains an internal oscillator and programmable PLLs and oscillator clock sources. Its core contains five sets of interrupted context selected registers and accumulators, which allows for faster interrupt response and has a fast six-cycle divide. The master and slave chips have 90-MIPS and 100-MIPS operation, respectively, and have independent peripherals. It comes in eight variations to allow for flexibility in design ranging from 28 pins to 80 pins and is available in packages as small as 5 x 5mm. The dsPIC33CH chip has a memory that ranges from 64 KB to 128 KB of flash.

dsPIC33CH demonstration
The Microchip website offers a video with a sample demo of the DSC controlling a motor. In the video, Microchip’s Tom Spohrer shows us how the two processors work independently and communicate with one another. The motor is adjusted to a speed via a potentiometer connected to the master board. The master board can then send this requested speed to the slave board via a core-to-core interface wherein the slave then handles the computations of the number of windings needed to achieve target speed.

The demo also shows that the master board can be reset while the DSC is running without affecting the motor speed of other functions. While this is happening, the slave board’s OLED also displays that the master board is being reset and continuously provides a reading of the activity of both boards. The chip also allows for low-power modes, sleep and idle, to conserve energy when not in use.

The demonstration is just an example that the dual-core DSC can handle sophisticated algorithms for motor control and various actuators while also accomplishing relatively simple hardware implementation. The dsPIC33CH is also designed for live firmware updating and, by receiving updates without shutting down, the microchip is particularly useful in applications such as in power supplies and other industrial technology in which there can be no downtime or else there may be a system failure.

The dsPIC33CH chip has been designed to allow for faster integration and less debugging without sacrificing data security. By allowing developers to work separately and integrating their coding on the dual-processing chip, debug times can be massively decreased. The dsPIC33CH datasheet can be downloaded here. The MPLAB Code Configurator (MCC) interface for setting up dual-core devices can be accessed for additional developer support.