By Gina Roos, editor-in-chief
Researchers at CEA-Leti and Stanford University said that they have developed a breakthrough non-volatile memory cell that has yielded a new circuit that integrates a multiple-bit NVM technology, called resistive RAM, or RRAM with silicon computing units. The new memory technology is said to provide 2.3× the capacity of existing RRAM and overcome NVM’s read/write, latency, and integration challenges.
The benefits of RRAM include storage density — packing more data into less space than other types of memory — energy efficiency, the ability to retain data when the chip hibernates, and the ability to be built on top of a processing circuit to integrate storage and computation into a single chip, explained Stanford researchers . But RRAM also comes with limitations in the areas of read/write, latency, and integration.
For the new chip, researchers improved the storage capacity of the RRAM — increasing the amount of information that each memory cell can hold — and developed an algorithm to overcome the write failure challenges, thus extending the lifetime of the chip.
The design of 2.3-bits/cell RRAM enables higher memory density, or NVM-dense integration, which yields better application results, said the researchers , delivering 2.3× better neural-network inference accuracy compared to a 1-bit/cell equivalent memory.
Image credit: Drea Sullivan Pexels/jéshoots.
Led by Stanford professors Subhasish Mitra and H.-S. Philip Wong and developed in CEA-Leti’s cleanroom in Grenoble, France, the chip integrates 18 kilobytes (KB) of on-chip RRAM on top of commercial 130-nm silicon CMOS with a 16-bit general-purpose microcontroller core with 8 KB of SRAM.
Some of the industry firsts demonstrated by the new chip include new algorithms that achieve multiple-bits-per-cell RRAM at the full memory level, the effectiveness of multiple-bits-per-cell RRAM at the computing system level, and new resilience techniques that achieve a useful lifetime for RRAM-based computing systems, said Mitra.
Researchers are targeting edge-artificial-intelligence (AI) applications such as energy-efficient smart sensor nodes for the internet of things (IoT). The proof-of-concept chip, announced at ISSCC 2019, has been validated for several applications, including machine learning, control, and security. The technology was presented in a paper, “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques.”
“Non-volatility, which enables memories to retain data when power is off, is becoming an essential on-chip memory characteristic for edge nodes,” said researchers. “The new chip delivers 10-times-better energy efficiency (at similar speed) versus standard embedded flash thanks to its low operation energy as well as ultra-fast and energy-efficient transitions from on mode to off mode and vice versa. To save energy, smart sensor nodes must turn themselves off.”
CEA-Leti and Stanford researchers also improved the inherent write failures in NVM technology, which can result in catastrophic results at the application level, they said. The team created a new technique called ENDURER that overcomes this challenge, delivering a chip with a 10-year functional lifetime when continuously running inference with the Modified National Institute of Standards and Technology (MNIST) database.
Although the current prototype is approximately the size of a pencil eraser, too large for many applications, it opens the door to make the next iteration of the chip “smaller, faster, cheaper, and more capable,” said Mitra, and “chip manufacturers are already showing interest in this new architecture.”
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