Three steps to optimize SiC power devices

By Maurizio Di Paolo Emilio, contributing writer

As new power transistors such as SiC MOSFETs are being increasingly used in power electronics systems, it has become necessary to use special drivers. Isolated gate drivers are designed for the highest switching speeds and system size constraints required by technologies such as silicon carbide (SiC) and gallium nitride (GaN) by providing reliable control over IGBTs and MOSFETs. The evolution of the architectures meets the new levels of efficiency and the stability of the timing performances, thus reducing the distortion of the voltage. This article uses ROHM Semiconductor’s power devices based on SiC technology as a reference point.

Why use SiC MOSFETs?
SiC technology can provide several types of benefits, as shown in Fig. 1 :

Fig. 1: Benefits derived from the adoption of SiC technology.

First, we have a lower intrinsic resistance of the material, which allows for smaller dice and ultimately smaller packages. This is a critical factor for complex components such as power devices, which generally include several layers in a bridge configuration. Moreover, a smaller die helps to optimize the internal layout better and reduces the parasitic capacitance.

A second benefit is a higher operative frequency. Higher working frequency, achievable through a better dynamic of the material and higher switching rate, allows the size reduction of passive components (coil inductors, filters, and transformers), the ripple, and, in some cases, the input and output capacitance.

A third benefit is related to the higher operating temperature due to the higher working temperature of SiC material (that can reach up to 200°C) and its better conductivity. Based on this, we can downsize the heat sink or, in some cases, simplify the cooling system. Sometimes it is even possible to migrate from a liquid to forced-air cooling system.

Challenges and optimization of SiC MOSFET driving circuits
Higher voltage:
The first point is related to the higher gate voltage. Fig. 2 shows a comparison among different power devices: a SiC MOSFET, a power MOSFET, and a silicon IGBT.

Fig. 2: Comparison of different power devices.

From the output characteristics (referred to different manufacturers), we can observe that there is high variability in the voltage level. ROHM SiC MOSFETs, now in their third generation, have a typical gate-source voltage (V_GS ) of 18 V. We are now interested in checking what happens if we drive a SiC MOSFET with an incorrect voltage level: We will start from 18 V, progressively reducing the voltage to 16 V, 14 V, and even below this. This aspect is essential because a voltage dropout can also happen in the field, caused by supply voltage variability or by other factors. A test was conducted in the lab using the setup shown in Fig. 3 :

Fig. 3: Test setup.

The measuring circuit is based on a booster configuration with an output power of 5 kW. Starting from a V_GS  of 18 V, the voltage is reduced step by step below 14 V. At 13.4 V, the test is stopped. Test results are visible in Fig. 4 . As expected, R_DS(on)  increases as the gate voltage decreases. At about 14 V (referring to the device under test), we can observe a dramatic increase of temperature, and the test must be stopped as soon as possible before a breakdown (due to thermal runaway) occurs.

Fig. 4: R_DS(on)  and gate voltage.

This phenomenon is known because the R_DS(on)  temperature coefficient inverts its sign at about 12 V to 14 V. At 18 V, the temperature coefficient is positive. This means that when the temperature increases, an increase of R_DS(on)  occurs. At a low gate voltage, however, the temperature coefficient is negative, and when the temperature decreases, the R_DS(on)  decreases. To avoid thermal runaway, a minimum gate voltage of 14 V is requested for some categories of SiC MOSFETs.

Another big question is how to drive a SiC MOSFET correctly and whether we can use a silicon MOSFET for this purpose. Consider, for example, the power supply schematics of Fig. 5 . With an input voltage of 700−1,000 VDC, it is tough to apply a silicon MOSFET, and in any case, we should use two MOSFETs in series to satisfy the voltage level for this application. The maximum voltage that the MOSFET can withstand can easily reach 1,350 V or above (1,000-V maximum input voltage plus the reflected voltage plus the surge voltage resulting from stray inductances).

Fig. 5: Driving a SiC MOSFET with a silicon MOSFET. A QR Flyback converter with three-phase input.

Instead of using two silicon MOSFETs, we could use just one SiC MOSFET (a 1,700-V type, for instance), but how to drive it? The answer is that we need a specialized IC. ROHM BD7682FJ is the first IC on the market optimized for SiC MOSFETs. It features a gate clamp at 18 V (avoiding a dangerous voltage), undervoltage lockout (UVLO) at 14 V, soft start (which helps to reduce the gate pulses), and a wide protection feature list.

Faster commutations:
Concerning IGBT transistors, SiC MOSFETs are known to have a better dynamic, which means faster commutations. SiC MOSFETs have some tens-of-nanoseconds commutation, compared to the IGBT with some hundreds-of-nanoseconds commutation. To achieve this fast commutation, we must provide the total gate charge in less time. That means that we need a higher peak current in the gate driver. How much higher? As shown in Fig. 6 , at least the same current of the IGBT is needed, or something higher.

Fig. 6: A SiC MOSFET offers faster switching compared to an IGBT. Due to faster switching time, SiC MOSFETs require a gate driver with a higher peak current.

Faster commutation also implies a higher dV/dt. Both dV and dt can be experimentally measured, as in the example shown in Fig. 7 ,where the IGBT and SiC MOSFET switching times are compared. As indicated in Fig. 7 , a gate driver with a common-mode transient immunity (CMTI) of at least equal to (or higher) 100 V per nanosecond is needed.

Fig. 7: A lower threshold involves a clean and low parasitic PCB layout.

Lower threshold:
An IGBT MOSFET has a threshold of about +5 V or even higher, whereas with a SiC MOSFET, the technology allows a lower threshold, about +1 V or +2 V (see Fig. 8 ). Moreover, this threshold decreases with increasing temperature due to a negative temperature coefficient for the threshold voltage. Therefore, in the gate driver design, we need to take care of this aspect because the noise on the gate can be dangerous. How can we control the noise and eliminate the parasitic effect? The first step is related to the PCB design. A good PCB design will minimize the following parameters:

• The impedance of tracks from OUT to gate to the capacitor
• The impedance of tracks from GND to source to the capacitor
• The area of the high current path (in Fig. 8 , the turn on the path is shown in red, whereas the turn off the path is shown in green)

Fig. 8: Miller effect occurring in a MOSFET half bridge.

The second step is related to the Miller clamp. Let’s consider the typical half-bridge MOSFET gate driver. A voltage change, V_DS , occurs across the lower switch when turning on the upper-side MOSFET of the half-bridge (M2: OFF → ON). This generates a current (I_Miller), which charges the parasitic capacitance C of the lower MOSFET (see Fig. 9 ). This current flows via the Miller capacitance, the gate resistor, and the C_GS  capacitance. The faster V_DS  switches from low to high. If the voltage drop across the gate resistor exceeds the threshold voltage of the lower MOSFET, a parasitic turn-on known as the “Miller effect” occurs (M1 turns ON).

Fig. 9: Active Miller clamping.

The Miller effect can be avoided in two ways. One is the negative power supply (VEE) used to keep the MOSFET off. The second one is active Miller clamping, shown in Fig. 10 .

This solution consists of the addition of a third internal MOSFET (M3) connected to the lowest potential in the driver circuit. When the MOSFET is being turned off, the clamp switch is activated as the gate voltage falls below a certain level to ensure that the MOSFET remains off throughout any ground bounce events or dV_DS /dt transients. As indicated in Fig. 10 , active Miller clamping can reduce a VGS increase by clamping the gate directly to ground or the negative power supply.

The third step is related to gate voltage oscillation. As you can see in Fig. 10 , oscillation can be both positive and negative, producing noise. A proven workaround, in this case, is to add a capacitor between gate and source to improve the C_GD /C_GS  ratio.

Fig. 10: An additional capacitor can reduce the gate voltage oscillation.

Because capacitors have an impact on switching time, this solution must be carefully evaluated. Based on the above-mentioned considerations, one device that meets these requirements is ROHM’s dedicated gate driver for SiC MOSFETs. The BM61S40RFV gate driver has UVLO at 14.5 V, overvoltage protection (OVP) at 22 V, a CMTI of 100 V/ns, and an output current of 4 A (it will be increased in future devices already planned in the product roadmap).

Conclusion
The foundation of the design is layout optimization. This is the first step to avoid parasitic components that add noise or spikes to the applied voltages or currents. The second step is the voltage level and the gate signal noise that must be checked under all operating conditions. The third step is to use dedicated devices for driving the SiC MOSFET.

This article was originally published on Power Electronics News .