Edge inference chip delivers higher throughput with a single DRAM

By Majeed Ahmad, contributing writer

Flex Logix Technologies has unveiled the InferX X1 edge inference co-processor that is optimized for neural-network inference. The chip delivers high throughput in edge applications with a single DRAM. This makes it highly suitable for low batch sizes in edge applications, which typically have a single camera or sensor.

The company said that the InferX X1 chip delivers near-data-center throughput at a fraction of the power and cost, delivering up to 10 times the throughput compared to existing inference edge chips.

The edge inference co-processor operates like an ASIC while it processes a layer on a data path using the reconfigurable interconnect. Then it quickly reconfigures itself and moves to the next layer. Here, InferX requires just a single DRAM — which cuts cost and power — because the local SRAM addresses most of the chip’s bandwidth needs.

The edge chip is built around the nnMAX neural inference engine that leverages the same interconnect technology used in the Flex Logix’s eFPGA design. The company combined the interconnect technology with multiplier-accumulators optimized for inference and aggregated them into clusters of 64 with local weight storage for each layer. This technology is ideally suited for inference applications because the eFPGA facilitates re-configurable data paths and fast control logic for each network stage.

The nnMAX inference engine is in development now and will be available for integration in system-on-chip (SoC) designs by Q3 2019. The InferX X1 chip will tape out in Q3 2019, with samples and PCIe boards available shortly after.