Renesas advances embedded STT-MRAM

Renesas Electronics Corp. has developed two new circuit technologies for an embedded spin-transfer torque magnetoresistive random-access memory (STT-MRAM) test chip with fast read and write performance. Fabricated using a 22-nm process, the test chip includes a 32-Mbit embedded MRAM memory cell array and achieves 5.9-nanosecond (ns) random read access at a maximum junction temperature of 150°C and a write throughput of 5.8-megabyte-per-second (MB/s).

The continued growth of connected devices, coupled with technology advances, is driving the need for next-generation non-volatile memory devices like MRAMs for MCUs used in IoT applications. But challenges still need to be overcome.

Embedded STT-MRAM test chip. Click for a larger image. (Source: Renesas Electronics)

Announced at the 2022 IEEE Symposium on VLSI Technology and Circuits in June 2022, Renesas has developed a fast-read technology that uses a high-precision sense amplifier circuit and a fast write technology with simultaneous write-bit optimization and a shortened mode transition time.

The advances were driven by the need for higher performance MCUs used in IoT endpoints, which require finer process node fabrication, as well as more efficient code writing to endpoint devices. The new circuit technologies are expected to boost memory access speed to exceed 100 MHz, which is currently a challenge with MRAM.

“MRAM fabricated in back end of line, or BEOL, is advantageous compared to flash memory fabricated in back end of line, or FEOL, for sub-22 nm processes because it is compatible with existing CMOS logic process technology and requires fewer additional mask layers,” said Renesas.

The challenge is that the “MRAM has a smaller read margin than flash memory, which degrades read speed,” in addition to “a large gap between the CPU operating frequency and the read frequency of the non-volatile memory since it can degrade MCU performance,” said Renesas.

The company also noted that further speed improvements are needed to shorten system downtime for over-the-air (OTA) updates for endpoint devices as well as to reduce costs in writing control codes for MCUs.

These challenges translate into a need for faster read and write operations in MRAM.

Renesas’s fast read technology uses capacitive coupling to boost the voltage level of the differential input nodes of the sense amplifier. This “allows the differential amplifier to sense a voltage difference even when the memory cell current difference is small, achieving high-precision and fast read operation,” said the company.

Renesas explained: “MRAM uses memory cells including magnetic tunnel junction (MTJ) devices in which high and low-resistance states correspond to data values of 1 and 0 respectively to store information. A differential sense amplifier distinguishes between the two states by reading the voltage difference in discharge speed between the memory cell current and reference current. However, since the memory cell current difference between the 1 and 0 states is smaller for MRAM than for flash memory, the voltage difference read by the sense amplifier is smaller. Even if the discharge time is extended to wider voltage differences between the differential input nodes of the sense amplifier, both of the input nodes are susceptible to being completely discharged before securing a necessary voltage difference. This problem is particularly acute at high temperatures.”

The high-speed write technology achieves even a higher speed than Renesas’s write technologies announced in December 2021 by shortening the mode transition time during write operation by approximately 30%.

“This technology divides up the areas to which write voltage is applied and, by inputting the write address before the write voltage setup, it selectively applies voltage only to the necessary area,” said Renesas. “This method reduces the parasitic capacitive load on the area where the voltage is applied during the write operation, reducing the voltage setup time.”