Ceva, Inc. has unveiled its fifth generation CEVA-XC DSP architecture, the CEVA-XC20, at Mobile World Congress (MWC) 2023. The CEVA-XC20 is based on a new vector multi-threaded massive compute technology that targets next-generation 5G-Advanced workloads in a variety of use cases. The new architecture can be used in smartphones, high-end enhanced mobile broadband (eMBB) devices (such as fixed wireless access and industrial terminals) and cellular infrastructure devices (such as base stations, virtualized DU accelerators and beamforming compute in Massive MIMO radios).
Thanks to the vector multi-threaded compute technology, the next-generation architecture increases power and area efficiency by up to 2.5× compared with the predecessor. As a result, SoC and ASIC designers using the CEVA-XC20 architecture can deliver smaller and lower power processors that have a positive impact on the environment, said the company.
Ceva said the new architecture was designed in consultation with its leading Tier 1 OEM customers with the goal of improving mobile network performance and power efficiency and solving the challenges of next-generation compute-intense 5G Advanced. The result is the novel Dynamic Vector Threading (DVT) scheme, which supports true hardware multi-threading.
Up until now it was only found in general-purpose CPU architectures, said Ceva.
What does DVT do? It enables the sharing of vector resources between different execution units for an efficiency boost in vector utilization. “This technique achieves optimal utilization of the VLIW architecture and improves core efficiency for common 5G execution kernels, as well as significantly enhancing use cases involving multi-component carriers and multi-execution tasks. This enables increasing the length of the vector processing units, usually consuming the bulk of the area in vector DSPs, while maintaining and even improving the execution efficiency relative to previous generations,” said the company.
Ceva’s CEVA-XC20 DSP architecture with DVT scheme (Source: Ceva)
Ceva also announced the first core based on the CEVA-XC20 architecture – the CEVA-XC22 DSP that supports two execution threads using the DVT scheme. The CEVA-XC22 offers up to a 2.5× improvement in efficiency (performance per watt and area) for 5G use cases and computation kernels versus its predecessor. It will be integrated into Ceva’s baseband platforms, the PentaG-RAN for cellular infrastructure and PentaG2-Max for high-performance mobile devices, powering the heterogeneous compute platforms, including both DSPs and compute engine accelerators.
The CEVA-XC22 DSP will be available for general licensing in the second quarter of 2023. The company’s Intrinsix team for ASIC/SoC co-creation services can help customers integrate the DSP and support system design and modem development.
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