SiTime launches clock generators for AI data centers

SiTime Corp. has unveiled its Chorus family of clock generators with integrated MEMS resonators for precision timing in AI data center applications. Called a MEMS-based clock-system-on-a-chip (ClkSoC) family, the Chorus clock chips offer 10× higher performance in half the size, compared with standalone oscillators and clocks. The family is comprised of the SiT91211 (150 fs) and SiT91213 (70 fs) devices.

Data centers use multiple precision timing devices for every instance of an application. These can range from one to three timing devices for every network interface card (NIC), up to eight to 24 timing devices for a single core switch.

(Source: SiTime Corp.)

SiTime takes a new approach with the Chorus family, integrating several components, including clock, oscillator and resonator technologies in a single chip. This simplifies the system clock architecture and accelerates design time by up to six weeks, according to the company.

A big driver behind this approach is AI in the data center with always increasing demand for higher data throughput and lower power consumption. Target applications include servers, switches, acceleration cards and smart NICs.

“Before Chorus, hardware designers had to use discrete product types, such as clocks, oscillators and resonators, which resulted in performance compromises,” said Piyush Sevalia, executive vice president of marketing at SiTime.

The Chorus clock generators with integrated MEMS resonators address several challenges with legacy clock generators, eliminating problems like noise and impedance mismatch between the resonator and the clock, as well as design delays, Sevalia said. These clock generators can also reduce the board area for timing by up to 50%. A single clock generator can drive up to eight single-ended output loads or four differential loads, replacing up to four standalone oscillators.

The Chorus clock generator family is packed with features. The SiT91211 and SiT91213 devices, housed in a 4 × 4-mm QFN package, include the resonator, oscillator circuit, PLL for the frequency multiplication and division, an on-chip regulator and non-volatile memory. They also offer flexible output types; up to four differential (LVPECL, LVDS, LPHCSL) or eight LVCMOS outputs, which are programmable; and a FlexSwing output that reduces power consumption and eliminates termination resistors.

The SiT91211 and SiT91213 offer low RMS phase jitter, 150 fs and 70 fs typical (12 kHz to 20 MHz), respectively. The 70-fs device targets higher-performance systems like 800G Ethernet, which requires better jitter, while the 150-fs device can be used in lower-performance systems like PCIe, where the jitter requirement is not as stringent.

These clock generators offer a flexible programmable frequency range from 1 MHz to 700 MHz as well as programmable voltage (1.8, 2.5 or 3.3 V). They provide I²C and SPI interfaces and are compliant with the latest PCIe standard (Generations 1 to 6).

Chorus family of clock generators block diagram (Source: SiTime Corp.)

Chorus is built around the concept of programmability, Sevalia said. “We want to make sure that the customer can program the devices how they want it to get the best performance out of the system and do it very quickly so that they don’t have delays or penalties.”

Other features include excellent frequency stability of ±20 ppm and ±50 ppm over the operating temperature range of –40°C to 105°C. These devices are also resistant to shock and vibration and offer EMI reduction thanks to the configurable spread-spectrum clock generation.

The clock generators also have a very good power supply noise rejection (PSNR), so it does not introduce more jitter from the noise on the power supply line. The PSNR is 10 fs/mV for both devices.

Use cases for the Chorus clock generators

There are two major use cases for the Chorus clock generators, Sevalia said. One use case is a printed-circuit board with multiple SoCs, each driven by an independent oscillator. This use case presents two problems: The layout area is larger and there is no synchronization between the different oscillators. The other use case is a system that uses a clock generator with an external discrete crystal resonator, where the trace between the crystal resonator and clock generator can generate noise.

How does the Chorus clock generator solve these problems? In the first use case, a clock generator, as a single device, can replace the functionality of the four oscillators and route the signals from the clock generator to the SoCs, providing a 50% savings in area, and it also provides the synchronization because all of these clocks will originate from the same PLL or the same reference, which is the resonator, Sevalia explained. For example, with a system that uses multiple Ethernet ports, the clock generator can be used to drive four, eight or 16 Ethernet ports from the same source, so they are synchronized to each other, he added.

In the second use case, any time there is noise on the clock line, the entire system clock will be impacted, and a second problem is that the impedance of the resonator must match the impedance of the clock generator and across multiple different clocks, Sevalia said. In many cases, customers send their entire system clock to the crystal resonator supplier for impedance matching, and that introduces a three- to four-week design delay, he added.

So the Chorus clock generator offers a smaller area and the synchronization of clocks, while the integration delivers higher performance and helps reduce the design time, which is why it is called a clock-system-on-a-chip, Sevalia said.

When compared with quartz clock generators, for example, in smart NIC applications with higher bandwidth and a fragmented clock tree, a single Chorus device can simplify the clock tree, Sevalia said. For enterprise switches with multiple oscillators and a complex power domain design, Chorus offers a smaller area and a single power supply domain to simplify the design. In PAM4 DSP with high-speed links, activity dips are a common problem with quartz crystals, which can lead to high bit-error rates, which is eliminated with the more stable clocks that Chorus offers, he added.

Problem solvers

The Chorus family also helps hardware designers shorten development time. A lot of the advantages of the Chorus family, including the resonator and clock matching (impedance matching), programmability and flexibility, such as making real-time changes in the system through the I²C or SPI interface, all shrink the design cycle. The clock synchronization also improves efficiency.

Another problem is the massive amounts of data processed by large language models, which translates into a need for higher-speed communications, and when the speeds are higher, the jitter needs to be better. The clock generator’s 70-fs RMS jitter solves this problem.

Another challenge is thermal gradients that come into play, especially in AI data centers, where things heat or cool down very quickly, Sevalia said. These devices are immune to environmental disturbers like thermal gradients, vibration and shock.

“The other benefit for the customer is that we are now a single source of all timing devices that they would need in a system, whether it’s resonators, oscillators or clock devices,” he added.

SiTime now offers a complete portfolio of timing solutions with the new Chorus product launch, combined with the recently acquired clock timing products from Aura Semiconductor.

“It was a natural space for us to expand into, and it’s keeping with our philosophy of solving problems for the customer,” Sevalia said. “And of course, it gives us more semiconductor content in the customer’s system.”

The Chorus family of clock generators is sampling to strategic customers now. General sampling will start in the second half of 2024.