Achieving extremely low power for portable apps

Achieving extremely low power for portable apps

Embedded MCU power management enables 20-year battery lifetime

BY JASON TOLLEFSON
Microchip Technology
Chandler, AZ
http://www.microchip.com

As more electronic devices become battery powered, conserving that power has become paramount. Recently, manufacturers of microcontrollers have added novel ways to control power consumption through various implementations of electronic switches. By removing power from parts of the chip, dramatic power savings are possible. Advances have also been made in voltage supervisory circuits so that they may be used continuously, consuming only tiny amounts of power.

Simply sleeping is not enough

Traditionally, reduced power consumption has been accomplished in applications by putting the MCU into sleep mode. This method has worked fine for many years, but there are several trends that are now converging that make this solution inadequate.

More complexity has been added to MCUs in recent years, along with the use of more advanced, and therefore leaky, process nodes. Combine this with the market need for 10 to 20-year battery-powered products and it becomes apparent that the traditional sleep mode is often no longer adequate. Extreme low power is now needed.

Counteracting the trends

Recently, manufacturers have added novel modes to their microcontrollers that offset the ill effects of increasing complexity and smaller process geometries. These modes might go by the name of LPM5, standby, STOP2 or deep sleep let’s refer to them as deep sleep.

Fig. 1. The PIC24F16KA XLP family is an example of MCUs employing deep sleep.

At the top level, the variety of deep-sleep implementations operate in the same way. Power is removed from significant areas of the chip using embedded software controlled switches. By powering off areas of the chip, the transistor leakage is removed and the battery life can be extended significantly. Figure 2 illustrates which circuits are typically enabled while in deep sleep all other circuits in gray are removed from power.

Fig. 2. Circuits enabled in deep sleep (green sections are on).

The degree of improvement derived from deep sleep varies by manufacturer, but 80% reduction in sleep current is common. In fact, some MCUs can now achieve a low as 20-nA draw while in deep-sleep mode. By combining low currents with batteries that have low self-discharge rates, deep sleep can add years to the life of an application.

Tradeoffs of deep sleep vs. sleep

With the benefit of dramatically lower current consumption comes a classic tradeoff. There is a longer startup time associated with deep-sleep modes. While wake from standard sleep was 1 to 10 µs, waking from deep-sleep modes can take 300 µs to 3 ms. This allows for power-up sequences to terminate and on-chip regulators to stabilize. Since power was removed from parts of the chip, exiting a deep-sleep mode behaves much like a power-on reset condition.

Most implementations of deep sleep remove power from RAM, peripheral registers, and I/O. This is quite different than standard sleep mode, where execution begins precisely where it was stopped. From deep-sleep modes, the program context must be restored from a non-volatile memory source, such as flash or EEPROM. Some manufacturers offer small “backup” RAM areas that are not powered down in deep sleep. Since code execution is required for this restoration step, there is a power penalty paid for using deep sleep.

So, the tradeoff for using deep sleep is longer wake-up times and the current used to restore the state before the execution was stopped. The good news is, however, that there are many applications that benefit from deep sleep in spite of the tradeoffs. When to use deep sleep and when not to can be understood using a simple calculation.

TBE = Breakeven time where charge in sleep equals charge in deep sleep

TINIT = Initialization time to resume full-power operation

IDD = Current consumed during run mode

TPOR = Time required for power-on reset

IPOR = Power-on-reset current (includes regulator stabilization capacitor current, if present)

IPDSLP = Static current in sleep mode

IPDDS = Static current in deep-sleep mode

This equation models the charge in sleep and deep sleep. The break-even time, TBE , is the point at which the charge in each mode is equal. Beyond TBE , deep sleep provides the maximum benefit. Example 1, below, illustrates this technique.

Suppose we have an MCU with deep-sleep mode that has the following characteristics:

Initialization execution time = TINIT = 200 µs

Current during execution = IDD = 400 µA

Power-on-reset time = TPOR = 600 µs

Current in POR = IPOR = 30 mA*

Current in sleep mode = IPDSLP = 3.5 µA

Current in deep-sleep mode = IPDDS = 28 nA

*30 mA includes current for regulator stabilization capacitor

So an application that can remain in deep sleep longer than 5.2 s will benefit.

Waking up from deep sleep

So, how do I wake up if I have removed power from most of the chip?

With traditional sleep mode, we had a variety of ways to wake up. They included interrupts, timers, communication reception, end of A/D conversion, supply-voltage changes and so on. Fortunately, MCU vendors have included many of these same features in deep-sleep mode.

Sources of wake-up available in deep-sleep mode can include: interrupts, reset pins, power-on reset, real-time clock alarms, watchdog timers, and brownout detection. Missing is wake from communication reception and end of A/D conversion since these portions do not have power. There is a wide gamut of wake-up source implementations among the different manufacturers and device families.

Some vendors only exit deep sleep by the assertion of the RESET pin. This is great for applications that have an “on” button and consume no additional current. It’s ideal for applications such as thermometers and handheld devices. Another use is for lengthening the shelf life of battery-powered products, by shipping them in the deep-sleep state.

For a more complete system implementation, some vendors have included more flexibility by adding real-time clock and calendar functions. This allows the application to be autonomous and can add as little as 500 nA to the deep-sleep current. This is very important for an application such as a smoke detector where it must wake 2 to 3 times per minute to sample the air quality, or a battery-powered sensor that wakes a few times per day to transmit data.

Application safety

As the battery is consumed, and we approach the its end of the useful life, the risk of improper operation increases. This issue is traditionally solved by the use of supervisory circuits, such as brownout reset (BOR) circuits and watchdog timers (WDT). These circuits usually consume as much as 5 to 50 µA and are therefore not compatible with the new deep-sleep modes.

However, recently, MCUs have added a variety of lower-current BOR and WDT circuits specifically designed for deep-sleep mode. Sometimes called deep-sleep BOR (DSBOR) or zero-power BOR, these brownout circuits offer diminished accuracy in return for outstanding current consumption as low as 45 nA. This capability is important not only for protection at the end of battery life, but also in the case of momentary power loss due to battery holder flex, a common issue. The implementation of low-current BORs varies from vendor to vendor, as some may be turned off and some are permanently on. Not all manufacturers of MCUs with deep sleep offer a BOR. Like BOR, the watchdog-timer currents have been reduced in MCUs with deep sleep. While only a few vendors have included WDT with deep sleep, the circuits can take as little as 400 nA.

With these advancements the combined current consumption can be as low as 445 nA 99% lower than the prior generation of MCUs. Now, using Equation 1 above, the break-even time (TBE ) with both supervisor circuits is only 5.9 s. Therefore, the current consumption of these new supervisory circuits facilitates safer applications for a whole host of applications that remain asleep longer than 6 s.

Through careful design of wake-up circuits and powering down wasteful parts of MCUs, vendors have thwarted the high-current leakage from shrinking process geometries to deliver sleep currents 80% lower than before. ■