ADC conserves FPGA I/O pins

The 16-bit 105-Mample/s LTC2274 ADC features a two-wire serial interface that reduces the number of data I/O lines required between a 16-bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single self-clocking differential pair communicating at 2.1 Gbits/s, freeing up valuable FPGA pins. Features include an SNR performance of 77.5 dB, an SFDR of 100 dB at baseband, and a power dissipation of 1.3 W from a 3.3-V analog supply.

The LTC2274 output data is serialized according to the JEDEC serial interface specification for data converters (JESD204) using 8b10b encoding, and is compatible with many FPGA high-speed interfaces including Xilinx’s Rocket IO, Altera’s Stratix II GX I/O and Lattice’s ECP2M I/O. Housed in a 40-pin, QFN package, the ADC also features internal transparent dither, data scrambler, and a clock duty-cycle stabilizer ($68 ea/1,000—available now.)

Linear Technology , Milpitas , CA
Information 408-432-1900
http://www.linear.com