Advanced ADCs bridge gap between A and D worlds

Advanced ADCs bridge gap between A and D worlds

Several major factors affect networking designers when choosing an ADC

BY ANDREW BENN
e2v, Grenoble, France
http://www.e2v.com

It doesn’t matter if you are a hardware designer, analog engineer, or a systems designer. With today’s tighter customer deadlines and worldwide competition, designers can’t afford delays in getting their products to market. As digital-processing horsepower continues its upward trend, analog designers are under close scrutiny to provide breakthrough solutions to unleash overall system performance.

The A/D converter (ADC) is undeniably one of the key components in networking and communications systems, providing the bridge between the analog and digital worlds. While logic engineers have reaped the benefits of improvements in digital-processing speed, power consumption, and footprint reductions, analog and systems engineers have been frustrated by the lack of similar improvements in ADC performance.

The A/D converter is the bridge between the analog and digital worlds.

Over the past few years, ADC performance improvements have been based on the component designer’s chosen silicon process and architecture guidelines that were often the extension of known design rules from previous ADC designs. This translated into modest improvements in ADC performance that were often targeting cost-driven applications. While system costs decreased, overall system performance suffered since the quantum leaps that systems engineers strived for were not met.

Performance improvements

The analog bottleneck caused by ADCs is being seriously examined and with some surprising results. ADC manufacturers have taken to task three ADC architectures that have in the past been targets for higher-speed networking and communications applications: an 8-, 10-, and 12-bit ADC.

In these types of applications, system engineers have weighed the pros and cons of dynamic performance (that is, the ADC resolution) versus the ADC’s ability to rapidly convert an analog signal (that is, the ADC data rate). By using sampling techniques such as undersampling or using digital post-processing, a designer can provide system performance equivalent to incorporating a higher-resolution ADC, but at a much higher data rate, typically in gigasamples/s.

An 8-bit high-speed gigasample ADC has been used in numerous networking and communications systems needing the ability to react quickly to changes to an analog signal in the time domain. Examples include specialty communications test equipment, digital oscilloscopes, high-speed data acquisition, radio-frequency identification (RFID), satellite modems, and satellite down-converters.

While dynamic performance of gigasample-per-second 8-bit ADCs are advancing, analog and system engineers are also benefiting from higher levels of integration and flexibility at board-level. Previous printed-circuit board layouts would include up to four 8-bit ADCs and associated DACs for interleaving controls or combining ADC chips to provide the higher gigasample-per-second data rate — as well as a microcontroller for necessary programming.

This system design was effective, but at the price of using critical board space and added power dissipation due to multiple components. Its major drawback was being dependent on the microcontroller performing regular (and often lengthy) calibrations during which the ADCs and the system were inoperable.

Turnkey solution

To offer a viable option to this classical board design, a turnkey solution is now available that integrates on-chip all necessary components (such as ADCs, demultiplexers, control DACs, crosspoint switch, programming capabilities, etc.). The results have been welcomed by the industry due to programmability on the fly via built-in standard SPI (serial programming interface) and the ability to adjust individual ADC cores for gain, offset, and phase (key parameters for interleaving multiple ADC cores) and still reduce overall system costs and board space thanks to significantly lower power dissipation.

In many high-performance networking and communications applications such as point-to-point microwave, WiMAX 802.16e, telecom test equipment, high-speed data storage, and software radio, ADC dynamic performance is one of the key driving forces in end-system requirements. It is one that engineers attempt to optimize in order to maximize their system performances operating at higher data rates.

This search for higher dynamic range, lower noise floor, and low-power consumption forces design engineers to look beyond an 8-bit ADC for many of their system requirements. In these instances, a high-speed broadband 10- or 12-bit ADC allows engineers to take full advantage of higher dynamic range and lower signal-to-noise ratio (SNR) for applications operating beyond baseband or IF sampling frequency regions. For a system engineer, a truly broadband ADC 10 to 12-bit or 14-bit solution is a key enabler in making the leap from an existing baseband or IF system design to a next-generation high-IF system design.

An example

To give an example, ADCs designed based on relatively narrow analog input bandwidths typically perform well at low input sampling frequencies (such as the 100 to 200 MHz). But as analog sampling frequencies increase, many ADCs’ performance suffer in rolloff of key performances such as dynamic range (SFDR) and noise (SNR, THD) characteristics.

For system engineers, techniques such as frequency down-conversion using multiplier analog stages allows their systems to sample higher analog input frequencies without needing a particular ADC to operate at these higher frequencies. The drawbacks are multiple analog stages needing multiple ADCs and related components, such as amplifiers, filters and combiners, which rob the board of valuable space, power, and precision and add system costs.

In addition, for systems needing higher data rates, designers must often make use of interleaving (or combining) two or more ADCs and in doing so, are confronted with unwanted spurs created in the digital domain that must be removed by the digital processor in the system, usually an FPGA. In making use of a non-interleaved or a single high-speed broadband ADC solution, system engineers can now free up processing power of FPGAs in their system by eliminating the need for spur removal in the digital domain. Because fewer components are used, a single gigasample-per-second ADC saves board space, greatly simplifies board layout, and lowers power consumption.

The solution is therefore a single ADC that provides a flat response in dynamic range and noise characteristics across a very wide analog input frequency range. A flat response relaxes the design requirements before the ADC, including the need for an amplifier and filter.

Due to a wide gigahertz analog input bandwidth, a single 10- or 12-bit ADC can simultaneously sample multiple broadband analog signals. This capability of doing more with less — providing higher end-system performance with fewer components and therefore simplifying a receiver-system architecture and reducing board costs — is one of the key enablers for a system engineer to make the quantum leap in networking and communications RF receiver designs. ■

For more on A/D converters, visit http://www2.electronicproducts.com/AnalogMixICs.aspx.