Advances in PoE Si enable higher power delivery, improved power management

Advances in PoE Si enable higher power delivery, improved power management

The new PoE PSE SoCs improve power dissipation, enable smart and agile power management for new distributed power-supply architectures

BY DANIEL FELDMAN
Microsemi, Irvine, CA
http://www.microsemi.com

The latest generation of high-power, IEEE802.3at-compatible PoE power sourcing equipment (PSE) increases power delivery from the 12.95 W of earlier IEEE802.3af-2003 standards to as much as 25.5 W over two-pair CAT5 cabling, and as much as 51 W over four-pair cabling. This enables PoE PSEs to power a significantly broader range of powered devices (PDs), ranging from 802.11n access points to IP video cameras and thin clients. These PSEs also improve power dissipation and management, and, with four-pair operation, allow for power delivery over even longer cabling lengths.

To maximize high-power PoE’s benefits, the underlying silicon must go beyond simple chip-level power efficiency to help improve overall system power budgeting. This requires a system-on-chip (SoC) approach with the intelligence to reduce power dissipation at the device, system and network level, depending on various PD characteristics. PoE SoCs also must deliver power management that is both accurate and agile.

PoE ICs power consumption depends on the technology being used, and how many ports are being served. In general, the logic section of four-port ICs use roughly three times more power than that of 12-port ICs. Of even greater significance, though, is that high-power 802.3at technology increases current from 350 to 600 mA, which creates challenges for PoE switch makers unless the underlying silicon delivers the proper capabilities. Earlier PoE PSE ICs built for IEEE802.3af had 2 Ω of Rsense and 0.5 Ω of RDS(on)(FET) , which meant that solutions dissipated 0.3 W/port in dc-disconnect on the resistors and FETs. In contrast, the latest smart PoE PSE ICs have much lower sense resistors (0.5 Ω) and also have external (or very low-resistance internal) FETs (0.1 Ω), which reduces power dissipation: 0.07 W/port in IEEE802.3af mode or 0.22 W/port in IEEE802.3at mode, for dc-disconnect (where supported).

Figure 1 shows a block diagram of a typical PSE SoC supporting IEEE802.3at. As can be seen, the MOSFET is controlled digitally, based on sensing the voltage drop on a resistor, which indicates the current passing through the FET.

Fig. 1. Typical block diagram for PoE PSE SoC for 802.3at.

In addition to minimizing power dissipation in high-power applications, today’s PoE PSEs also must deliver highly responsive and agile power management, so that they can dynamically allocate power, as needed, in today’s distributed power-supply architecture. In earlier architectures, a single, large power supply was used, and dissipated power even when not fully employed — an enormous energy drain. For instance, a 48-port switch with 800-W full power per port might use only 20 ports at any given time, wasting as much as 80 W of quiescent power.

To solve this problem, the large power supply can be replaced with a smaller, more economical internal default power supply that is augmented by external power supplies for incremental additional power. The resulting, distributed power architecture improves overall system efficiency, enables prioritized per-port backup power, and reduces heat dissipation and cost because of the smaller supply and associated smaller and/or lower-speed fans.

To implement this architecture and manage several power supplies simultaneously, there must be a way to accurately measure power consumption, and a means to dynamically allocate power. PoE ICs with very fast reaction times are required in order to manage the overall power budget. Power allocation can be performed dynamically, according to how much power is consumed by the device, or in a static or pseudo-static approach, using hardware classification or the new IEEE802.3at-2009 layer 2 classification for communication between the device and the PSE. This type of fast reaction can normally not be done by a central CPU, this requires allocated resources.

Benefits of four-pair operation

Four-pair operation is another key aspect of the IEEE802.3at-2009 standard. IEEE802.3at-2009 creates two types of devices — Type 1 and Type 2 — and does not preclude collocating these two devices on the same Ethernet cable, which means power can be delivered over all four pairs of Ethernet CAT5 cable. There are several benefits associated with this change.

First, by delivering power over all four pairs of CAT5 cable, up to 51 W of power can be delivered to each PD, which enables PoE to power a much broader range of PDs. The four-pair configuration improves efficiency as compared to two-pair products, since four-pair powering enables 60 W to be delivered with a low, 600-mA current level rather than the 1.2-A level of a two-pair approach. In other words, for the same 60 W at the source, 51 W can be delivered over Cat5 cable via four-pair solution, as compared to 42 W for two-pair solutions.

Second, this same four-pair configuration can be used to power two-pair devices with 30 W of power, while dissipating up to half the power and consuming almost 15% less energy than conventional two-pair solutions. This translates into savings of approximately $25/year per powered device, assuming energy costs of $0.10/kWh. All of this is possible because the IEEE802.3at-2009 standard considers the PD the power interface, as opposed to the whole device being powered. This means that one can have two power interfaces, each taking 25.5 W inside the same box. And nothing precludes these to be connected — one over the two pairs using lines 1, 2, 3, and 6, and the other using the two pairs that use lines 4, 5, 7, and 8. This is what makes it possible to double the standard 802.3at-2009 maximum of 25 W and go up to 51 W while fully complying with the standard.

Finally, the four-pair configuration offers the opportunity to extend cabling lengths. Type 1 devices assume the same legacy cabling infrastructure (Cat3) that was the minimum required for IEEE802.3af-2003. So, if Type 1 devices are used with worst-case Cat5 cables, the cables could actually be 60 percent longer. The resistance of the Cat5 cables is equivalent to Cat3 cables (see Table 1 ), or 480 ft. Of course, this scheme would only work if the physical-layer (PHY) device being used to transmit data could also support these long distances.

Table 1. Resistance of Cat5 and Cat3 cables

For Type 2 devices, there is still a lot of flexibility when assuming worst-case Cat5 cabling infrastructure. As long as the input voltage to a PD is 37 V or higher, and the current is below 600 mA, the PD will work with cables longer then 300 ft, and the PSE will behave any differently. This is because the PSE monitors, by default, the load of the cable, and considers the PD to be a single entity. Table 2 shows that, as long as a PD consumes no more than 22.8 W, a 480-ft cable can be used.

Table 2. Cat5 cable lengths and power restrictions

The latest smart PHYs can actually measure the cable length. For instance, Microsemi’s PD690xx PoE PSE Manager can allocate power correctly to a PD, when the cable length and PD maximum power requirement are known. The benefit of this is that A PD that needs more then 22.8 W from the PSE over a 480-ft cabling length will not get disconnected unexpectedly when it gets to maximum load. More power is dissipated on the cable than normal, since the power dissipation concentration in such a system is the same as that used over 300-ft cabling lengths. But the same 100-cable bundle used in normal systems can be used in this scenario. IEEE802.3at PSEs offer a variety of benefits, all enabled by PoE PSE SoCs that improved power dissipation, enable smart and agile power management for new distributed power-supply architectures, and support for four-pair operation to deliver higher power levels and longer cabling lengths. ■