Altera: Nios II Network Acceleration Reference Design
This reference design illustrates how to achieve high bandwidth network connectivity in a Nios® II soft-core processor based system. This design makes use of an accelerated networking media access control (MAC) from MorethanIP, with built-in check-summing and direct memory access (DMA) support, and an optimized networking stack from InterNiche Technologies, which implements zero copy support. A Nios II processor is used for application control and packet processing.
The design is deployed on the Nios II evaluation board , featuring a Cyclone TM EP1C12 FPGA. Features Nios II soft-core processor MorethanIP MAC-NET 10/100/1000 Mbit MAC InterNiche Technologies NicheStack IPV4 networking stack Deployed on the Nios II evaluation board, with a Cyclone EP1C12 device.
Features
• Nios II soft-core processor
• MorethanIP MAC-NET 10/100/1000 Mbit MAC
• InterNiche NicheStack IPV4 networking stack
• Deployed on the Nios II evaluation board
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