AMD expands FPGA portfolio

AMD has unveiled its low-power Spartan UltraScale+ FPGA family, the newest addition to the company’s Cost-Optimized FPGAs and adaptive SoCs. The new power-efficient Spartan FPGAs claim the industry’s highest I/O to logic cell ratio in FPGAs built in 28-nm and lower process technology. They also provide hardened connectivity and advanced security features. Applications include embedded vision, healthcare, industrial networking, robotics and video.

(Source: AMD)

Optimized for the edge, the Spartan UltraScale+ FPGAs offer high I/O counts and flexible interfaces to enable easier integration and more efficient interfacing with multiple devices or systems. They offer up to 572 I/Os and voltage support up to 3.3 V. Packaging starts as small as 10 × 10 mm.

The Spartan UltraScale+ family offers up to a 30% lower total power consumption compared to the 28-nm Artix 7 family via 16-nm FinFET technology. They are the first AMD UltraScale+ FPGAs with a hardened LPDDR5 memory controller and PCIe Gen4 ×8 support.

New security features focus on protecting IP, preventing tampering and maximizing uptime. They include support for Post-Quantum Cryptography with NIST-approved algorithms for state-of-the-art IP protection against evolving cyber-attacks and threats. PPK/SPK key support manages obsolete or compromised security keys and differential power analysis helps protect against side-channel attacks.

The FPGAs also feature a physical unclonable function providing each device with a unique fingerprint and enhanced single-event upset performance, offering fast and secure configuration with increased reliability.

The AMD FPGAs and adaptive SoCs are supported by the AMD Vivado Design Suite and the  Vitis Unified Software Platform. Spartan UltraScale+ FPGA family sampling and evaluation kits will be available in the first half of 2025. Documentation is available today with tools support starting with the AMD Vivado Design Suite in the fourth quarter of 2024.