ARM enterprise building blocks

At the Linley Processor Conference in Santa Clara, ARM introduced CoreLink CCN-508 Cache Coherent Network IP that offers scaling to 32 processor cores to give system architects a great solution for enterprise applications including servers and network infrastructure. The IP runs at 1.5 GHz in the 28 HPM process and has a 1 to 32 Mbyte L3 Cache and quad DDR-3/4 interfaces. It has a deadlock free AMBA-5 CHI basis and a cycle accurate system C performance model. The CCH-508 enables a usable system bandwidth of >1.6 Tbits/s with Cortex-A57, -A53 processors.

The AMBA 5 protocol enables the latest ARMv8 64-bit architecture Cortex-A50 series processors to work together in high-performance, coherent processing hubs of >12 CPUs.

Also introduced was the CoreLink DMC-520 5^th generation, dynamic memory controller designed for an optimal solution for enterprise applications including servers and network infrastructure.