ARM Introduces LPDDR2 Memory Controller to Accelerate Chip Performance and Improve Energy Saving

ARM Introduces LPDDR2 Memory Controller to Accelerate Chip Performance and Improve Energy Saving

Updated ARM DDR and DDR2 memory controllers offer DDR PHY (DFI) Interface support

CAMBRIDGE, UK – Oct. 7, 2008 – ARM [(LSE: ARM); (Nasdaq: ARMH)] today announced the ARM PrimeCell low-power DDR2 (LPDDR2) dynamic memory controller (PL342), which provides a high-performance interface to LPDDR2 memory systems that provide more than twice the bandwidth of LPDDR memory systems and deliver significant power savings over standard DDR2 memory.

The PL342 memory controller complements ARM’s existing broad range of memory controllers and Physical IP and will enable SoC designers to take full advantage of LPDDR2, particularly in applications such as mobile multimedia, networking and consumer applications, which require high bandwidth access and low power consumption, and have multiple bus masters which require access to shared memory. LPDDR2 memory is emerging as a compelling solution for next-generation mobile and embedded applications and ARM has been an active participant in the JEDEC committee defining the LPDDR2 standard.

The ARM PL342 dynamic memory controller offers a highly configurable interface between the AMBA 3AXI™ protocol and LPDDR2 memory, tuning the memory interface to provide breakthrough efficiency, managing transactions through arbitration and scheduling, delivering quality of service (QoS) support, and minimizing latency in memory access to maximize system-on-chip (SoC) performance. Further, the PL342 memory controller features numerous energy-saving functions, including partial and full power-down and pre-charging of memories without affecting data flow.

The PL342 memory controller’s modular design enables it to be adapted for use with many types of dynamic memory. Future releases will add support for additional memory types to provide optimal solutions for current and planned CPU and GPU cores.

ARM is a contributing member of the industry consortium defining the DFI (DDR PHY Interface) specification, and the PL342 memory controller will be an early adopter of the DFI 2.1 specification. The DFI compliant PHYs being developed by the ARM Physical IP division will enable ARM PrimeCell memory controllers to provide improved processor performance while simplifying design implementations.

The PL342 memory controller is one of a number of new additions to the ARM memory controller family, all of which will support DFI. Other new additions include:

a new version of the popular PL340 DDR/LPDDR dynamic memory controller offering LPDDR-NVM support

a new version of its PL341 DDR2 dynamic memory controller, featuring ECC (Error Correcting Code) support – a critical feature for automotive and networking applications.

“As LPDDR2 memory becomes more widely available, designers will be looking for new ways to bridge the performance gap between external memory and SoC processors, and take full advantage of advanced low-power memory systems. The ARM PL342 dynamic memory controller helps to maximize memory interface efficiency, minimize latency and ensure QoS, while minimizing energy consumption,” said Keith Clarke, VP Fabric IP, ARM. “ARM is committed to continued innovation in interconnect and peripheral IP to deliver integrated, optimized solutions for SoC backplanes.” ■