By Bruce Swanson, Mentor Graphics
As integrated-circuit device geometries get smaller, the blah, blah, blah … How many times have you read a conference paper or article that started out this way? I know I’m guilty of writing some of them. The blahs usually explain how much harder it is to do this, that, or the other thing.
Bruce Swanson, Mentor Graphics
By Bruce Swanson, Mentor Graphics
As integrated-circuit device geometries get smaller, the blah, blah, blah … How many times have you read a conference paper or article that started out this way? I know I’m guilty of writing some of them. The blahs usually explain how much harder it is to do this, that, or the other thing. These include items like getting design timing closure, mask preparation and manufacturing of the actual semiconductor, and testing the die or packaged parts for the critical ICs that are prevalent in PC hardware and other applications. As I work in the area of creating software that allows semiconductor companies to test their manufactured ICs for defects, I’d like to explain what is going on in the realm of testing as the device geometries continue to get smaller.
The history of testing computer chips is rooted in functional tests. Back when the logic gate count of the devices was something you could count on your own fingers and toes, it was not too daunting of a task to create some tests that could be run on the chips by placing known values on the input pins and then observing the resulting output pin values to determine if the circuit was operating correctly. But as semiconductor processes aimed to put more logic into a smaller chip, it didn’t take long for the device gate counts to grow dramatically. So while the idea of functional test was still attractive, the reality of actually creating and debugging the tests by hand became overwhelming and expensive.
Scan design was a method developed to simplify the test creation process. By changing the design’s flip-flops into scan cells and adding a small amount of test logic, the design had many more control and observation points. The next logical step was automation in the form of automated test pattern generation (ATPG) tools. ATPG tools don’t functionally test the device logic, but rather check the design for manufacturing defects by creating test patterns based on fault models
Fault models mimic the different defect mechanisms that show up in ICs. The most basic and widely used fault model is called stuck-at. For each cell or gate pin in the logic design a stuck-at-1 and stuck-at-0 fault is used. The stuck-at test can find many types of defects, including: nets tied to power or ground, bridging between two or more nets, and open nets.
As the device geometries got smaller, new types of defects were appearing or became more prevalent. For example, at the 130-nm node more timing related defects were showing up. A timing defect might be caused by a partially formed via or other anomaly in the physical implementation of the IC. To test for these types of defects requires a timing based test instead of just the static stuck-at model. The transition fault model is a good choice to test for these types of defects. With the transition model, faults are added to each cell or gate pin to check that this location can switch from a logic 0 to 1 value, or vice versa, within the specified clock period.
Timing Fault Models
Another timing fault model is called path delay. To use this model, the user generally uses a static timing analysis tool to determine which paths are most critical (least amount of slack time) in the design. These critical paths are entered into the ATPG tool so it can create test patterns for those specified paths.
These three fault models — stuck-at, transition, and path delay have been around for a number of years and are widely used in industry as the basis for a good test pattern set. But what is happening in designs when they reach 90-nm, 65-nm, or even smaller process nodes? Well, one thing is that more bridging defects can occur due to the physical layout and very small spacing between nets. Also, since the nets themselves are much narrower than in the past, open defects can also happen more readily.
Leading design companies are employing, or at least exploring, some newer fault models for improving their production test quality. These models include multiple detection, small delay, and layout-aware tests. Research into these and other new models continues at the ATPG companies.
The multiple detection model is more of a methodology change while creating the test patterns instead of being a completely new model. In fact, it is done with either the stuck-at or transition fault model. Rather than dropping a fault from the fault list when it is covered by a test pattern, the fault is not dropped from the fault list until it is captured a specified number of times. Most users choose to use a number between 3 and 5. This methodology provides an improvement in the probability to detect some defect types, like bridges.
As a variation of the basic transition fault model, the small delay model is a timing test that checks the design for the smallest possible delay defects. It does this by creating transition type patterns that try to use the longest possible paths. To accomplish this, the ATPG tool uses the actual timing information from the completed layout data to calculate and find the best (longest) paths that can be used for each fault when creating the test patterns.
The last topic we’ll cover here are layout-aware tests. These require a physical extraction tool to analyze the actual chip layout for areas that are more prone to have defects. The extraction tool uses specified rules to check for features that could cause potential bridging net pairs or open locations. Once those nets or locations are identified, they are used within the ATPG tool with the appropriate fault models to create test patterns to target these areas.
So to help you fight the blahs as IC device geometries get smaller and smaller, consider the types of defects that you are likely to encounter. Then determine which fault models to use in ATPG to keep your test quality as high as possible in manufacturing test. It is much better for you to catch defective ICs than for your customers to find them.
About the Author
Bruce Swanson is a Technical Marketing Engineer in the Design-For-Test division at Mentor Graphics. He received an MS in applied information management from the University of Oregon and a BS in computer engineering from North Dakota State University. Bruce has over 20 years of experience in EDA and computer hardware design.
Check out the Mentor site for details of its product offerings at Mentor
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