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At ISSCC: A 100-W microprocessor, a 1-in.-plus DRAM
Along with more-expected advances in microprocessor technology, this
year's International Solid-State Circuits Conference in San Francisco*
will feature the first microprocessor with triple-digit power dissipation.
Other papers will describe CMOS and GaAs devices, all in the possibly
air-cooled realm. In all, about 90 papers will be presented. The
high-power chip, from Digital Equipment's Western Research Lab in Palo
Alto, CA, is ECL and runs at 300 MHz in the laboratory. The 32-bit chip
carries 468,000 bipolar transistors and 206,000 resistors made in a 1.
0-micron process. On-chip data and instruction caches are 2 Kbytes each.
The die is completely covered with 1-mil-thick gold bus bars that
distribute 26-A supply current. The chip is probably destined to upgrade
VMS customers with large VAX clusters to the Alpha architecture. It seems
unlikely that such a chip could ever be a merchant semiconductor product.
ISSCC attendees will also hear about another chip to reach 300 MHz. This
one is a 16-bit video signal processor from NEC and Chuo University, in
Japan. The specialized chip encodes CCITT H.261 CIF video at 30 frames/s.
In GaAs, the University of Michigan will report on a 32-bit RISC processor
with 160,000 transistors on a 13.9 x 7.8-mm chip. The processor dissipates
24 W at 200 MHz. In addition to an ALU, the chip has a 32 x 32 register
file, 4-word write buffer, 128-byte instruction cache, and management for
two levels of off-chip instruction and data caches. For pure ALU speed,
another processor to be described manages an add in only 1.5 ns. The 0.
25-micron CMOS device, from Hitachi Central Research, runs at 2.5 V using
double pass-transistor logic.
Memory In the memory area, Toshiba, Hitachi, and NEC will all present
256-Mbit dynamic RAMs. The latter two are fabricated with a 0.25-micron
geometry, and NEC's has a 30-ns access time. The Hitachi chip is 33.2 mm
long. It has some on-chip repair capability. The first 256-Kbit DRAMs
reported some years ago had redundant rows or columns, with laser-repair
capability. However, as production ramped and prices tumbled, repair
became out of the question, as it probably will again. CMOS static RAMs
achieve 16-Mbit densities this year, in 0.25- and 0.35-micron processes.
Access times go below 10 ns (under lab conditions). IBM, hanging in there
with mainframe hardware, has a 1-K x 16 bit ECL dual-ported cache RAM. .
Its access time is 1.2 ns for a read-write port and 1 ns for the other
port, which is read-only. A 256-Kbyte cache made of these would burn close
to 500 W.
Technology directions Technology Directions, which is a mixed-bag
session, formerly called Emerging Technologies, makes room for papers
either not specifically backed by silicon produced in the past year or not
represented by enough papers for a full session. Quantum Electronics,
represented in two papers, promises enormous circuit density with
resonant-tunneling diodes and transistors. Fuzzy-logic processors also rate
two papers in the session.
Evening panels Among the evening panels one of near-term interest will
hash out the competing fast DRAM standards, RAMbus DRAMs, cached DRAMs,
RAMlink DRAMs, and synchronous DRAMs. Another will try to project what
microprocessors will be like in the year 2000. Video compression
architecture is a hot topic right now, with several major players vying
for attention and dollars. –Rodney Myrvaagnes
* For more on ISSCC at the San Francisco Marriott from February 24 to 26,
call Courtesy Associates in Washington, DC, at 202-639-4255.
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