Axcelerator offers high performance at densities of up to two million equivalent system gates. Based upon the Actel AX architecture, Axcelerator has several system level features such as embedded SRAM (with complete FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic.
The Axcelerator family consists of several advancements: Control circuitry that supports high-performance communications design; Fracturable SuperCluster for high logic module utilization; Embedded 64-bit PerPin FIFO that enables easy interfacing with off-chip resources on different clock domains; Core Tile structure for tighter clock skew across the device; and a flexible clock structure with eight PLLs and eight global clocks available equally across the chip.
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