Bit-error-rate tester exposes jitter completely

Bit-error-rate tester exposes jitter completely

For high-speed interfaces such as PCIe 2.0, USB 3, and FB-DIMM 2, instrument permits robust designs with tighter margins

Said to be the only instrument to offer complete jitter tolerance testing for the highest-speed digital interfaces, the J-BERT N4903B serial bit-error-rate tester lets engineers accurately characterize and compliance-test next-generation devices based on multi-gigabit serial buses up to 7 or 12.5 Gbits/s. Thus the BERT lets designers create robust products with tighter margins than previously possible.

The unit not only works with interfaces such as PCIe 2.0 and USB 3, but also forward-clocking ones like QPI, Hypertransport 3, and FB-DIMM 2. It characterizes jitter tolerance and margins of receivers using forward-clocking architectures by providing half-rate clocks with variable duty-cycle distortion to emulate effects of nonideal clocking, and letting users inject jitter on the forwarded half-rate clock and on phase-adjustable data signals.

The BERT has a full range of integrated, calibrated jitter sources with selectable random jitter that includes PCIe 2.0-compliant spectral distribution, single- and two-tone periodic jitter, spread-spectrum clock and residual SSC, BUJ, built-in ISI, and sinusoidal interference.

For accurate TJ measurements, it has built-in CDR with tunable loop bandwidth. Further, it can adapt to a DUT by emulating idle conditions and sourcing variable-voltage-level trigger and aux data outputs. It also has a 60-block pattern sequencer for fast execution of long test sequences. (7-Gbit/s unit, from $139,000; 12.5-Gbit/s unit, from $179,000, upgrades from N4903A — available March.)

Agilent Technologies , Santa Clara , CA
Sales 800-829-4444
http://www.agilent.com