Boundary-scan standard eases board-level testing

BY CASPER STOEL
Alternative System Concepts, Inc.
Windham, NH

Each advance in the level of circuit integration has made bed-of-nails testing
more difficult. The traditional method for testing pc boards in production was
developed at a time when boards contained fewer devices and interconnections.
ICs-with their ever-growing pin counts-have made it physically difficult to
place test probes at all the necessary points on a board.

The boundary-scan test standard was created to meet the challenge of testing
complex boards. In 1987, a group of electronics and semiconductor manufacturers
from around the world formed the Joint Test Action Group (JTAG) to begin work
on a standards-based solution. The result of their efforts was the
boundary-scan standard, officially referred to as the IEEE Standard Test Access
Port and Boundary-Scan Architecture. It is more commonly known as IEEE 1149.1
or JTAG.

The standard effectively puts test probes and circuitry inside an IC,
providing access to the chip's inputs and outputs through a simple interface.
Primarily intended to ease board-level testing, boundary scan also provides
capabilities for remote diagnostics and device-level testing. Of course,
boundary-scan testing requires that test criteria be considered during device
design rather than board design. However, synthesis tools, created with JTAG in
mind, minimize the effort required by IC designers to implement the standard.

A basic description
Boundary scan allows for full observability and controllability of all
primary inputs (PIs) and primary outputs (POs) of a device with only four or
five additional pins. The four mandatory pins are Test Data In, Test Data Out,
Test Mode Select, and Test Clock. The optional fifth pin is an asynchronous
Test Reset. The low pin count is possible because instructions and data are
scanned in and out serially.

A boundary-scan register (BSR) is basically a long shift register with one
shift element (boundary-scan cell) for every pin (see Fig. 1a ). A typical
boundary-scan cell can observe data on the input of the cell (coming from
either the core or the PI), shift data, and control data on the output of the
cell (going to the PO or into the core) (see Fig. 1b ). If any delay on the PI
is unacceptable (like a clock signal, for example) observe-only boundary-scan
cells, which are also part of the standard, can be used.

Another module described in the standard is the Test Access Port (TAP). A
finite-state machine, the TAP controls the scan circuitry, the instruction
register, and the bypass register. Optional registers for device identification
and data are also controlled by the TAP. Three instructions are mandatory in
the standard: Sample/Preload captures data on the input or preload data on the
outputs; Extest applies data at the outputs; and Bypass bypasses the device's
BSR.

Benefits of the methodology
Although boundary scan was developed to test board-level interconnections, it
has brought about several additional benefits. When combined with internal scan
or built-in self test (BIST), boundary scan lets the user verify operation of
the device itself. It can also be helpful when performing diagnostics on a
device, allowing inputs and outputs to be observed and modified.

In all cases, boundary scan provides access to the device without direct
physical contact.
It also has value in protecting intellectual property, offering a standard
interface to proprietary test features, like internal scan and BIST.

The need for boundary scan is most apparent in situations where probing is
difficult if not impossible. Equipment exists to probe and test components such
as high-pin-count ICs and miniscule surface-mount devices, but its cost is very
high. For a fraction of that cost, a design could incorporate boundary scan and
still permit access to every pin.

Of course, not everyone designs high-pin-count devices in small packages.
However, many designers are involved with system-level designs. Often, this
means that if a single device fails, someone must navigate through a hierarchy
of racks, boards, and devices to diagnose the problem.

Even if a system includes diagnostic capability to locate a faulty board,
just the act of removing the board from the system and delivering it onto the
diagnostician's desk may be more expensive than adding boundary scan to each
device in the system. Besides, with boundary scan it might not even be
necessary to leave one's desk. With test circuitry embedded in the design,
diagnostics may be performed remotely by modem.

Boundary scan's economic benefits extend to maintenance of the product
through its entire life cycle. As for design overhead, boundary scan represents
just 2% to 10% of the design area, depending on circuit size.

The role of synthesis tools
Boundary scan requires that test requirements be considered during a device's
design. In fact, the earlier in the design cycle that boundary scan (and other
test features) can be added, the better. Fortunately, some of the boundary-scan
test synthesis tools work at the register-transfer level (RTL), which helps
avoid design iterations due to area and timing constraint violations. Also,
these tools perform better optimizations than tools working at the gate level.

Control circuitry for boundary scan can be custom-generated, instead of using
a one-size-fits-all control block. The RTL approach can actually save area by
creating only as much control circuitry as is really necessary. Another
optimization easily performed at the RTL is the connection of the device's
other test features to boundary scan, providing a complete high-level picture
of a device.

There is yet another reason to insert boundary scan at the RTL-it might be
the designer's only chance to do so. The use of an RTL floorplanner may make it
impossible to add boundary scan later in the design flow.

Synthesis tools have simplified the process of inserting boundary scan and
verifying compliance with the standard. These design tools can automatically
insert and connect boundary scan in a design and create a test bench to verify
that the functionality of the inserted circuitry agrees with the standard.

Synthesis can also be used to create a boundary-scan description language
(BSDL) file. The BSDL file is a functional description of boundary-scan
circuitry that can be used by board-level test-generation tools. It
contains the boundary-scan interface, available instructions and op
codes, instruction length, and boundary-scan register. The boundary-scan
description language is a subset of the VHDL standard IEEE 1076 and is
sometimes referred to as IEEE 1149.1 supplement B.

Boundary-scan test synthesis tools require only a basic familiarity with
boundary scan. The designer does not need in-depth knowledge of the standard to
implement it. Although RTL tools are technology independent, some designers may
be concerned with the mapping of boundary-scan components to available cells in
an ASIC library. Again, design tools help the user obtain optimum results by
offering a mechanism to map boundary-scan cells directly to library components.

CAPTIONS:

Fig. 1. Boundary scan provides access to a device's inputs and outputs through
a five-wire interface and a test access port that controls-scan circuitry (a).
A boundary-scan cell can observe and control data flowing into and out of the
device core (b).