Calibre PERC from Mentor Graphics

The Calibre PERC IC verification tool project was started via a customer request a couple of years ago. PERC’s ability to mix and match physical, logical, and electrical checks, combined with the ability to be programmed to look at certain areas of the design for a certain type of problem, makes this tool special. But combining IC design-rule checking (DRC) with other facets of the design is something many companies have taken a pass at, including many startups focused in this area. Mentor Graphics’ product ended up being special because of several factors that happened just right.

Fedor Pikus, Chief Architect and Greg Hackney, Engineering Manager, told us that a cross-discipline design team, combined with a number of experts from various internal development groups that were pulled in as needed, were key elements in their success. The freedom provided to team members to explore various ideas was also cited.

Some of the Mentor Graphics design team (from left to right): Top Row: Sridhar Srinivasan, Greg Hackney, Carey Robertson, Padmaja Susarla; Bottom row: Patrick Gibson, Fedor Pikus, Ziyang Lu.

Interestingly, when the project started the team went out to customers to get their opinion, and the customers, for the most part, said no, the tool isn’t necessary and it won’t help us, it has been tried before and never worked, and just don’t bother with this project. But the team felt they had some core pieces of the puzzle and persisted.

PERC is especially useful with the current need for analysis of ESD problems in I/O circuitry and for detecting connection violations when there are multiple power domains. There have been numerous success stories where customers were able to find electrical errors that were not caught elsewhere and where previous scripted verification flows took 20+ hours to run and PERC was able to accomplish the same thing in just a few hours.

Jim Harrison