ZYCAD.SEP–rp
Can conventional ATPG meet today's testing needs? n Until
conventional test tools truly become a turnkey solution, test tool vendors
and ASIC designers may need to rely on customized test services to stay
competitive
BY SUBHENDU GUPTA Protocol, the Services Div. of Zycad Corp. Rockaway,
NJ
The dramatic increase in the use of application-specific ICs in the 1980s
sparked a new awareness of test issues. The introduction of top-down
design methodology–with hardware description languages, logic synthesis,
and mixed-level simulation–into mainstream design enabled designers to
implement complex ASICs that were previously inconceivable. Such
complexity pushed test issues to the forefront. Engineering managers began
to demand a coherent and well-defined test strategy from the outset of the
design cycle. This complexity also gave birth to scan-based automatic
test program/pattern generator (ATPG) tools. These tools evolved into a
means for creating and evaluating test stimuli targeting these complex
electronic circuits. ATPG tool use has covered the spectrum from
single-chip ASICs to multichip board-level designs. Now increasing
complexity is contributing to changing testing again, as are the expanding
use of ASICs, collapsing product life cycles, shrinking market windows,
and the demand for improved quality. Self-testability is gaining
popularity because of the escalating cost of field-repairs and the demand
for higher performance. As a result, conventional scan-based ATPG tools
have started to lose momentum.
ATPG drawbacks and promises Scan-based ATPG tools suffer from an
inherent bias toward structural digital designs with little or no support
for BMODs AUTHOR: PLEASE DEFINE or analog/mixed-signal circuits.
Furthermore, chip-level test problems are spilling into the pc-board
domain. Specifically, testing tightly packed boards comprising multiple
ASICs and/or advanced IC packages–for example, tape-automated bonding,
and quad flatpacks–has become a serious problem because of the limited
topological accessibility of such tools. ATPG tools have also fueled the
expectation of a push-button solution to test generation, but have not
delivered effectively on that expectation. The future of ATPG tools is,
however, far from bleak. Even with the rising popularity of various
built-in-test methodologies within the new design-for-test (DFT)-conscious
community, conventional ATPG tools still provide the most reliable form of
deterministic pattern generation and structured fault grading. What these
tools need, based on the emerging design methodology requirements, is to
re-focus on the market demands (see chart). To keep pace with these
diverse trends, ATPG tools must provide a wider range of support for
standardized design and test vector interfaces (for example,
VHDL/Verilog/EDIF, and TSSI), standard libraries, test generation for
behavioral architectures, and increased vector compaction and efficiency
rates. How well a specific ATPG tool addresses each of these categories
also depends on its level of dependency (or lack thereof) on other CAE tools
such as fault simulators, signature analyzers, and testers. Although a
precise analysis of an ATPG tool's effectiveness is less than objective,
their usefulness nevertheless can only be well understood from test
experience. Unfortunately, most companies cannot afford to spend the
lead-time required to evaluate the vast number of commercial test tools
and select the best possible match. In most cases, test is still an
afterthought to design specification, and the issue is frequently left to
the designer's discretion. There is little doubt that most designers have
an aversion to DFT, as it lies outside their traditional “comfort zones.”
Furthermore, there is no absolute requirement from the ASIC vendors to
produce an easily testable design. The result of these constraining
factors is an ad hoc approach to both testability and the test tool
selection process. No matter how appropriate a tool may be, its
deficiencies are magnified enormously when improperly implemented and
integrated into the product development cycle. Potential users need access
to available guidelines for selecting tools that best fit their
testability requirements, guidelines on how to incorporate a proven test
methodology into their product development process, and assistance in
specific testability implementation and vector generation techniques. The
answer to these emerging test needs may lie in a rapidly growing segment
of the EDA marketplace: electronic design test services (EDTS). These firms
offer a wide variety of custom consulting services ranging from test tool
selection and training, through testability analysis and recommendations,
to test generation and fault grading. These organizations also offer their
customers the manpower needed to bridge the deficiencies in the selected
toolset and meet their specific design and test needs.
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