The next frontier in battery technology: Rechargeable lithium
The next frontier in battery technology: Rechargeable lithium Good energy density and discharge characteristics could make lithium good for portable products Research on
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Massive Alpha microprocessor has level-2 cache on chip
Massive Alpha microprocessor has level-2 cache on chip Recent microprocessor disclosures include the 21164, an Alpha implementation that let Digital Equipment Corp. (MA)
Metaflow Technology reappears with silicon
Metaflow Technology reappears with silicon Not heard from since LSI Logic dropped the Lightning, the company has a three-chip superscalar Sparc with speculative
Public/private effort presages next-generation CAD/CAM/CAE
Public/private effort presages next-generation CAD/CAM/CAE A collaboration between Applied Engineering Services (AES) and the Army Research Laboratory (ARL) and
HDL simulation: Key to concurrent verification
HDL simulation: Key to concurrent verification New EDA tools allow complex electronic designs to be verified from initial concept to production BY DAVID ALLENBAUGH
For high-information-content displays, the world is flattening
For high-information-content displays, the world is flattening Flat-panel technologies jockey for position in the race to replace CRTs as the high-information-content
Software simulators speed the entire design cycle
Accelerate VHDL simulation and the entire design cycle BY BRIAN CASLIS and JIM KENNEY Mentor Graphics Corp. Wilsonville, OR The new generation of software VHDLContinue
GaAs MMICs for wireless transceiver components
GaAs MMICs for wireless transceiver components The tradition of handcrafted discrete RF designs is giving way to more economical MMIC solutions BY CHARLES HUANG
Another way to build stacked memory chips
Another way to build stacked memory chips Stacking wafers to produce 3-D memory chips has become a popular way to achieve higher packaging density. TheContinue
New frame-buffer architecture renders 1.8 million triangles/s
New frame-buffer architecture renders 1.8 million triangles/s A new architecture specific to graphics frame buffers is said to render 1.8 million 100-pixel triangles/s,