UPDATE.JUL--Motors and Controls--pm Product Update: Motors and Controls This sampling of recently introduced motors and controls is indicative of the small size, high
ADAPTEC.JUL–wy SCSI test systems are changing More complex SCSI peripherals and bus configurations are placing new demands on SCSI testers BY THOMAS W. MARTIN
BENCHTOP.JUL–benchtop power supplies– SC– Page Benchtop power supplies meet diverse testing needs More instruments allow either local or remote control
Telecom library for DSP design The Telecom Simulation Library is a data-driven communications library that consists of fully parameterized and programmable block models.
Tool synthesizes active RC filters FilterMaster Active is a PC-based tool for designing and analyzing active RC filters. It allows users to synthesize complete
Toolset breaks design entry bottleneck FlowHDL is a graphical design entry and verification toolset for ASIC, FPGA, and PLD designers. The toolset allows designers
Tool simulates both VHDL/Verilog The ViewSim/HDL simulator enables electronics engineers to simulate Verilog HDL- and VHDL-based designs within a single environment. The
Timing analyzer for high-level design DesignTime is a standalone timing analyzer for high-level design that provides static timing analysis within the native design
System design tool is improved Version 2.5 of the ExpressV-HDL graphical design tool for system level ASIC design supports IEEE standard MLV 9, has moreContinue
Place-and-route tool for million-gate ICs GARDS IV is a high-performance IC physical design product that provides automatic placement and routing of VLSI and ULSI