Chip-stacking technology uses off-the-shelf die

OL2.NOV– Nov–DPM–SC

Chip-stacking technology uses off-the-shelf die

In their quest to improve packaging density, semiconductor packagers are
increasingly looking up–that is, at stacking chips. Several months ago,
Irvine Sensors Corp., Costa Mesa, CA, announced its Memory Short Stack
(Electronic Products, July, p. 21). Now, another company, Dense-Pac
Microsystems of Garden Grove, CA, has announced the latest generation of
its 3-D stacking technology. Dense-Pac's approach uses a substrate called
a stackable chip carrier. It differs from Irvine Sensors' approach mainly
in that it can build stacks from off-the-shelf, pretested production die.
Irvine Sensors, on the other hand, uses custom-built wafers that are first
separated into individual die and then stacked. In the Dense-Pac
stackable chip carrier (see photo), the die is attached active side up, to
the bottom of the substrate. A large bonding window in the substrate is
used to wire-bond the die to the substrate above. This bonding window is
filled with epoxy to secure the bonding wires. The die thickness is
reduced before the electrical testing and environment screening.
Afterwards, the fully tested and screened substrate is ready to be
programmed, using a wire bond, for its location in the stack. The chip
carriers are then stacked and epoxied together. The stack is solder dipped
to make the vertical traces used to interconnect the substrates. The
stackable chip carrier can be designed to accept any silicon technology
and allows mixing of different memory types within a stack. For a typical
commercial application, the stack is mounted on a lead frame and molded in
plastic. In a military or industrial application, the stack would
typically be hermetically sealed in metal or ceramic. The stackable chip
carrier can also be used to mount silicon on multichip module substrates.
Density achievable with the stackable carrier is impressive. Sixteen
megabytes of DRAM can fit a pc-board area just 0.448 in.2 By
comparison, using SO-J packages to achieve the same capacity would require
3 in.2 of board space, while using SIMMs would still require over 1
in.2 Along with improved density comes reduced board size and
complexity, as well as less parasitic inductance. For more information,
contact Norman Taylor at Dense-Pac Microsystems, Garden Grove, CA, at
714-898-0007, or . –Spencer Chin

CAPTION:

The stackable chip carrier from Dense-Pac Microsystems uses off-the-shelf
production die stacked and bonded together.