Choosing the right timing device for your system

Choosing the right timing device for your system

Understanding your application specifications is the most critical step

BY KEVIN CHANG
Cypress Semiconductor
San Jose, CA
http://www.cypress.com

Every electronic system irrespective of size or complexity needs a timing reference to run the board circuitry. These clocks are the heart of the system, giving the board a steady pulse from which to operate by. However, it is also one of the last devices placed on the board. For such a critical and time-to-market sensitive device, the clock is given little more than an afterthought.

This article will walk engineers through the intricacies of selecting a timing device earlier in the design cycle; from understanding which type of clock is right for the design (crystal, crystal oscillator, or silicon-based) to understanding which features (spread spectrum, in-system-programmability, field programmability) to consider. It will help readers understand the benefits of each device, and will provide guidelines for how to measure the true characteristics of a device.

Understanding your application specifications

Gathering information about the timing requirements is the most critical step in developing the best timing subsystem. It is important to look at the entire board at once, noting all of the frequency requirements; with clock integration, traces routed from one source can fulfill multiple device requirements.

Determine the frequencies (MHz), voltage requirements, signaling type (LVCMOS, LVDS, or LVPECL), and jitter specs for each. If you are redesigning a board, determine if there are any crystals or crystal oscillators on the old design that can be integrated.

Note any special requirements such as VCXO or spread spectrum if these are already known. Armed with this information, we are ready to determine a basic timing architecture.

First we need to determine if a clock IC or a discrete solution would best fit the design. Take a look at the board’s frequency requirements. If any of the following apply, then an IC clock should be considered:

• There is more than one clock signal required

• The frequency is higher than 50 MHz

• The frequency is nonstandard

• There are potential electromagnetic interference (EMI) problems on the board

• There is still volatility in the design.

If the board only requires one very standard frequency, then a discrete device such as a crystal oscillator may provide the best value. However, with the advancement of phase-locked-loop (PLL) design, silicon timing devices now offer considerable advantages over discrete devices for most systems.

These advantages include lower failure rates in comparison to discrete crystals; the ability to synthesize nonstandard and greater-than-50-MHz frequencies without added manufacturing overhead or the use of expensive higher order overtone crystals; the effects of crystal aging which causes long term frequency drift; EMI reduction capabilities through spread spectrum; and programmability for design, testing, and use flexibility. In the next few sections we will walk through choosing an IC device, and we can compare which will provide the best value.

Clock ICs are segmented based on the number of PLLs that have been integrated into the design. Each PLL allows the engineer to generate an unrelated frequency. Clock ICs also integrate frequency dividers, which allow each PLL to generate signals which are multiples of each other.

Additionally, many ICs incorporate pins which allow the PLLs to be dynamically reconfigured. Depending upon the system, this may affect the number of PLLs needed. For many systems, choosing a multi-PLL clock allows integration of crystals, crystal oscillators, and other ICs, thus saving board space.

Clock ICs also allow designers to reduce EMI by a significant margin through a technique called spread spectrum. EMI must be below limits set by regulatory standards such as FCC Part 15 Class B, CISPR 22, VCCI, and EN55022.

All consumer products must pass through stringent regulations in order to be released into the market. Spread spectrum reduces peak energy of high-speed signals by dampening the harmonic resonance of a steady signal. Additionally, spread algorithms such as Lexmark profiling can further reduce peak energy with only minimal spread percentages. Because of the significant redesign effort involved when a system fails an electromagnetic compliance test, it is often a good idea to incorporate a programmable spread-spectrum clock as insurance before the testing stages in order to minimize redesign and time-to-market risks.

Spread spectrum reduces peak energy of high-speed signals by dampening the harmonic resonance of a steady signal.

After determining the number of PLLs required and whether a spread-spectrum clock would be a good fit for the system, the next important step is to get into the particulars of the system. The timing device must be able to meet the signaling type, voltage requirements, and jitter specifications of the devices they are supplying.

For consumer markets, the industry standard is a 3.3-V LVCMOS signal. However, many current silicon clocks are equipped with differential signaling, and some provide output banking for voltages down to 1.8 V.

On top of that, silicon timing devices are offered in extremely small packages. For instance, Cypress has More Baterry Life (MoBL) clock devices that not only boast significantly reduced power consumptions, but the ability to fit a 4PLL programmable spread-spectrum clock in a small 4 x 4 QFN package.

For years, designers had to make do with fixed function devices with fixed frequency multiplication, standard spread percentages, and set buffered outputs. While these allowed for multi-sourced devices, they did not cater to each individual design and so only provided suboptimal results. Only for high-volume products were companies able to justify the costs of custom masks, which still take several weeks to manufacture and sample.

Programmability provides flexibility in both the design and testing phases of product development. The input frequency and type can be adapted and PLLs can be programmed to provide different outputs for board changes.

Spread-spectrum percentages and output drive strengths can be modified to meet FCC regulations. These changes can be made in minutes instead of the weeks it would take for a custom crystal or masked IC solution. Devices can programmed before being soldered to the board or field programmed. Some clock ICs use I2 C programming to program the clock’s volatile memory during startup.

Beyond flexibility, programmable devices also provide advantages once the system goes to mass production. A programmable clock can provide IP protection for systems that may be susceptible to IP theft. Programmable clocks reduce inventory management, not only through BOM integration, but also because one clock can be made to service many separate platforms through I2 C or on-chip registers. Distribution partners also tend to stock more of these devices because they can service multiple customers with a handful of devices, reducing lead times.

Programmability also allows the designer to manipulate more pieces of the clock IC than they previously had access to. For example, system designers can now test how a system responds to overclocking.

Pins can also be used as output enables, and PLLs can be powered down for applications where power is an issue. Engineers can use PLL cascading to ensure 0-ppm accuracy in cases where synthesis is very difficult and accuracy is crucial.

They can also enable glitch-free switching for on-the-fly configuration. Any of the PLL and divider values can be manipulated to affect outputs frequencies, accuracy, and jitter. It is also possible to test the system for linear and Lexmark spread profiling to see which gives the best EMI reductions, as well as testing outputs for center spread versus down spread to see how the system reacts. By having access to all of the clock’s programmable features, designers have the tools to build a robust solution specific to the system requirements which can enable better performance and reduce failures.

In the end, each timing device is as unique as the system design. Designers should compare multiple types of devices to determine which would provide the best value. Understanding how to maximize value through integration of discrete timing devices and EMI-reducing devices will reduce costs, inventory management, and board space.

Designers should also understand how programmability can reduce time to market both through design flexibility and as insurance during testing while also providing the most customized and robust solution. The clock is the heart of the system, so it is important to devote time to determine the best approach possible.