Renesas Technology (San Jose, CA) is developing a next-generation CISC architecture for 16- and 32-bit microcontrollers that is said to provide revolutionary enhancementsa reduction in code size by 30% and CPU power dissipation by 50%.
Based on the company’s 90-nm flash process, devices using the new architecture will have up to 4 Mbytes of memory and run at 200 MHz. They will have more general-purpose registers for higher throughput, new complex instructions for improved execution efficiency, variable byte length instructions, and improved compiler optimization.
The cores will feature gating clock technology along with reduced flash memory read current and are expected to require only 0.04 mA/MHz. The development project also stressed efficient and easy-to-use software development environments, effective debugging tools, and compatibility with existing products. The specifications of the new CPUs will be released in early 2008, and the first devices using the new design are expected in the second quarter of 2009. For more information, visit http://www.america.renesas.com.
Jim Harrison
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