Clock multiplier ICs synthesize any frequency

Clock multiplier ICs synthesize any frequency

Industry’s first such parts have 0.3-ps jitter performance, rivaling traditional analog PLLs

Presented as the industry’s first jitter-attenuating clock multiplier ICs, the Si53xx family can generate any output frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from any input frequency between 2 kHz and 710 MHz. Its 0.3-ps jitter performance rivals traditional analog PLLs built discretely using expensive VCXOs or voltage-controlled SAW oscillators.

The Si53xx features an integrated loop filter with selectable bandwidth, a low-phase frequency-agile VCO, a phase detector, a divider, and buffers. Additionally, the Si53xx family supports up to four clock inputs and five differential clock outputs, eliminating the need for external multiplexers and clock distribution buffers traditionally used in complex timing subsystems of modern communications equipment. The Si53xx family consists of four any-rate clock multipliers (Si5322, Si5325, Si5365, and Si5367) and five any-rate clock multipliers/jitter attenuators (Si5316, Si5323, Si5326, Si5366, and Si5368). (From $12.10 to $72.45 ea/1.000available now.)

Silicon Laboratories , Austin , TX
Leslie Palmer 512-532-5382

http://www.silabs.com