Clock translator supports many wired network apps

Clock translator supports many wired network apps

The AD9559 dual adaptive clock translator is offered as the most flexible high-performance device of its kind for high-density line cards and OTN applications. The part synchronously converts any standard input frequency to any standard output frequency at up to 1.25 GHz with sub-400-fs RMS total jitter over a 12-kHz to 20-MHz integration bandwidth.

The device replaces two synchronous timing devices with a single IC, helping designers with board space constraints and cost optimization. Adaptive clocking allows the DPLL (digital PLL) divider ratios to be changed while the DPLL is locked. This enables the frequency at the output to be dynamically adjusted over a ±100 ppm range, around the nominal output frequency, with a resolution in frequency step as low as sub-0.1 ppb, without breaking the loop and reprogramming the part. Each of the two DPLLs can be synchronized to one of up to four input references, and each DPLL generates two output clocks.

The part supports GR-1244 Stratum 3 stability in holdover mode, ITU-T G.8262 Synchronous Ethernet slave clocks, and ITU-T G.823, G.824, G.825, and G.8261. It also supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 Systems.($19.26 ea/1,000 — available now)

By Christina Nickolas

Analog Devices , Wilmington , MA
Sales 800-262-5643
www.analog.com