CMOS transistors achieve quad data rate via oversampling
Researchers at NEC Electronics (Santa Clara, CA) have achieved quad-data-rate transfers from the same CMOS transistors previously used for double data rate. In a recent ISSCC paper, the researchers reported a test demultiplexer, in conventional 0.18-µm technology, that could receive and decode 10 Gbits/s over a serial line, using demultiplexer transistors clocked at 2.5 GHz. Four integrators in parallel, clocked at 90° phase intervals, sample the input stream. Each individual sample window spans two bits of the input, in a process analogous to the oversampling converters in portable CD players. Whenever the new input bit is the same as the previous bit, it is clear whether it is 1 or 0. However, if the sample encompasses a 1 and a 0 the value in the accumulator is the same, so the new bit is undetermined. The output of any one integrator is thus an ambiguous three-valued logic. The ambiguity is resolved by reference to the value of the integrator that was open for the previous phase (see diagram ). If, say, the previous integrator had 1-0 or 0-0 and the new integrator holds 1, the new result is 0-1.
In this quad-data-rate recovery scheme, each half-cycle of the four-phase sampling clock spans 2 bits of the serial input, using the previous result to resolve 1-0/0-1 combinations.
In the pathological case of a stream 10101010101010 . . ., the system fails; but such a stream carries no information. The stream must include 0-0 or 1-1, and as soon as it does, the decoding works from then on. The experimental chip lacked clock-recovery facilities, so an external PLL was used to generate the four-phase clock. Future process technology should allow the technique to reach 40-Gbit/s transfers before CMOS runs out of steam, according to the company. The value of keeping such operations in CMOS lies in the increased possibility of integrating it with the rest of a large SoC circuit, and fending off a move to a more costly multichip solution.
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