CN-0302: Ultra-Fast Settling PLL with RF to 13 GHz block diagram

CIRCUIT FUNCTION AND BENEFITS
The PLL circuit shown in Figure 1 uses a 13 GHz Fractional-N synthesizer, wideband active loop filter and VCO, and has a phase settling time of less than 5 μs to within 5° for a 200 MHz frequency jump.
The performance is achieved using an active loop filter with 2.4 MHz bandwidth. This wide bandwidth loop filter is achievable because of the ADF4159 phase-frequency detector (PFD) maximum frequency of 110 MHz; and the AD8065 op amp high gain-bandwidth product of 145 MHz.
The AD8065 op amp used in the active filter can operate on a 24 V supply voltage that allows control of most wideband VCOs having tuning voltages from 0 V to 18 V.

CIRCUIT DESCRIPTION
In a PLL and VCO frequency synthesis system, achieving less than 5 μs frequency and phase settling time requires a very wide loop bandwidth. The loop bandwidth (LBW) defines the speed of the control loop. A wider LBW allows for faster settling time, at the expense of less attenuation of phase noise and spurious signals.
The circuit in Figure 1 operates by locking the ADF4159 to the RFOUT/2 signal (~6 GHz) of the 12 GHz VCO (MACOM MAOC-009269). However, VCOs up to 24 GHz that have a RFOUT/2 signal can be used with the ADF4159, since it accepts RF inputs up to 13 GHz.

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