Compression & security coprocessor handles 40 G

The XR9210, XR9225, and XR9240 compression and security coprocessors provide 10, 25, or 40 Gbits/s throughput with simultaneous compression, encryption and hashing. The IC has a PCI Express 3.0 host interface supporting 64 Gbits/s with eight lanes and a 40 G Interlaken interface for an FPGA connection.

The chip detects Class of Service to prioritize traffic for critical applications and has single root I/O virtualization (SRIOV) with 128 virtual functions to support virtualized I/O. It has support for gzip, zlib, Deflate, and eLZS compression and a wide range of symmetric and asymmetric encryption algorithms. It can perform 40,000 operations/sec of RSA with 2048-bit keys. Now sampling.