1998 Product of the Year Award Winner
Configurable µC brings on-chip-peripheral
choice to low-volume designs
The E5 Configurable Processor System Unit (CPSU) is the forerunner of
a new class of devices–a standard microprocessor core combined with a
RAM-based FPGA–that promises small companies seamless integration of ad
hoc derivative microcontrollers. This capability was until now only available
to designers with the budget for system-on-chip ASICs. Such designers have
already been able to pick through libraries of available functions and
incorporate them in specialized designs.
A development system called FastChip is a critical element of the CPSU
design flow. It allows the user to “drag and drop” IP peripherals
from the company's library to create derivative chips.
The programmable portion of the chip has up to 3,200 Configurable System
Logic cells (about 40,000 gates) and up to 64 Kbytes of RAM. The internal
bus transfers at 40 Mbytes/s and allows standalone operation with one external
memory that holds both program and configuration data.
The E5 uses an 8032 core, enhanced with four-cycle instructions and
running up to 40 MHz. It is joined to the FPGA section–the bulk of the
chip–by a proprietary bus that will be used for other processor cores
in the future. The ARM7TDMI core is the next to receive this treatment,
via an agreement with ARM licensee Sharp Microelectronics (Camas, WA),
which will fabricate that chip in its 0.25-µm CMOS process.
The first E5 chip, the TE520, has 2,048 cells, 40 Kbytes of RAM, and
251 user I/O cells. The second, the TE505, with 8 Kbytes, 512 cells, and
123 I/O, will sample this quarter and is projected to cost under $8 in large
quantities by the year 2000. (TE520, $55 ea/100–samples available now.)
Triscend
Mountain View, CA
Chris Balough 650-968-8668, ext. 140
Fax 650-934-9393
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