Consumer wants drive portable media architecture

Consumer wants drive portable media architecture

The decisions on how to partition the system are among the most important a designer will make

BY PAUL WILSON
Wolfson Microelectronics
Edinburgh, U.K.
http://www.wolfsonmicro.com

The pressure continues for designers of portable multimedia devices (PMDs) to incorporate more features into ever smaller products with longer battery life, fast time to market, and at low cost. New capabilities, such as high-fidelity sound, video cameras and color displays, rely on increasingly sophisticated mixed-signal ICs.

At the same time, digital semiconductors, such as DSPs, memory chips, and microprocessors, are being driven to smaller geometries in order to save cost, space, and power. In a perfect world, we could integrate virtually all functionality onto one system-on-chip (SoC), but for the foreseeable future that’s not economically feasible.

Partitioning systems

Many of the features that end-users demand require cost-effective high-performance analog and mixed-signal functions. As a result, many designers are beginning to recognize that decisions on how to partition their systems are among the most important that they make.

For some applications a case can be made for a high level of integration with an SoC, while other applications may be best served with a complete discrete solution. Many, however, are best implemented using a few highly integrated ICs.

The choice rests on a balanced tradeoff among features, cost, time to market, flexibility, power consumption, and design complexity. Figure 1 shows a typical mobile handset block diagram. Although some handsets and other PMDs will have different feature sets and thus a different block diagram, this is representative of a medium featured handset with high-end audio capabilities.

Fig. 1. This medium-featured handset has high-end audio capabilities.

Integration

If a design team is tasked with developing an ultra-low-cost handset, it’s clear that the way to achieve this is to have the highest level of integration. By implementing an SoC, designers reduce board real-estate requirements, cut system cost, and lower power consumption.

Cost as the No. 1 goal will drive certain tradeoffs, most notably time to market, flexibility, and analog performance. Typical design times for a complex SoC could be greater than one year, and mask-set costs are also very high, encouraging designers to really do their homework before taping out an SoC. Flexibility will be limited since an SoC has a defined feature set and adding too many programmable options both goes against maintaining low cost and lessens the probability of first-pass success of the device.

However, there is a limit to what can be practically integrated onto one SoC when cost and performance are taken into account. The economic case for continually moving digital circuits to smaller geometries is well known. On the other hand, mixed-signal and analog functions benefit little from process shrinks.

For example, Wolfson Microelectronics recently undertook a study looking at the dynamics of shrinking an existing design from 0.35- to 0.18-μm technology. The original chip was (by silicon area) 40% digital, 40% analog, and 20% pad-and-scribe typical figures for a modern mixed-signal device. The shrink to 0.18 µm yielded a substantial drop in the size of the digital circuits, around 75%.

However, without further optimization, the area figures for the other parts of the circuit remain more or less unaffected. The total area reduction is on the order of 30%. Working purely on the basis of die costs, the shrink therefore makes sense only if the price premium for moving to 0.18 µm is less than 30%.

The sheer range of functions that need to be integrated into a fully featured media device, such as a portable media player, also provide a barrier to integration. Digital core voltages are now as low as 0.6 V, though generally the need remains to provide additional 1.8- and 3.3-V power supplies. From a battery management point of view, the system will undoubtedly need to deal with the 2.7 to 4.2-V levels produced by a Li-ion power pack.

Voltage requirements

Adding peripheral interface functions adds additional voltage levels. USB connectivity requires 4.2 to 5.5 V, while TFT display drivers typically use 12 V. Achieving the signal-to-noise ratios required by high-quality audio necessitates the use of 2.7 to 3.6-V supplies, but generating speaker power of the order of 1 W per channel requires the use of voltages as high as 5.5 V.

Not only do these differing voltage requirements lead to high levels of complexity for the SoC designer, they also make for a chip that is not easy to fabricate. Such a device requires multiple transistor geometries on the same wafer — perhaps as many as four. As a result, manufacturing and testing become correspondingly more difficult, the wafer cost increases and yields drop.

Based on the tradeoffs noted above, the large SoC may be practical if only the digital functions are included or if very-low-end analog performance is needed.

Discretes

On the other end of the spectrum, designing a family of top-end handsets with high-performance audio and other high-end features could be accomplished by using a variety of discrete components. This allows the selection of the best components to meet the requirements.

The all-discrete approach enables designers to quickly produce handsets with various features allowing product differentiation. On the downside, an all-discrete approach likely will increase the cost, size and power consumption of the handset.

Unfortunately, the real design requirements are often more than just cheapest or most full-featured, they are somewhere in between. This necessitates a different design approach. An approach must be found that can support designing a family of products with various feature sets, yet still maintain the levels of audio playback performance and capabilities that users expect while providing long battery life and small size.

Meeting the demands

A design methodology that can meet the demands of fast time to market, high-end performance, scalability to multiple product versions while maintaining battery life and minimizing size, is to implement the whole system in the correct combination of technologies.

Comparison of different design methodologies

Products such as PMPs or handsets can be broken down into a number of subsystems. The fundamental digital control and signal processing functions should be implemented in the most advanced process available, running at a core voltage down to as low as 0.6 V. The choice of memory implementation, typically mobile DDR running at 1.8 V, may require its own optimized process technology.

In the peripheral field, RF circuitry typically has its own requirements, which may be satisfied by an RF CMOS process or by more specialized GaAs or SiGe devices. A further special case is the implementation of display drivers, with their 12-V supply requirements. These are typically realized using chip-on-glass techniques.

A generic mixed-signal technology, capable of taking in a range of functions including USB and Ethernet interfaces, voice codec, touch screen interface, speaker/headphone drivers, hi-fi codecs and power management, must also be added. These fit comfortably together on a single devicewith the possible use of an industrial standard interconnect such as the Mobile Industry Processor Interface (MIPI) consortium’s serial low-power interchip media bus (SLIMbus).

An example of this level of partitioning is shown in Fig. 2 . The main components in this IC are the audio codec, battery charger, power management, and control functions. This implementation could result in savings of 50% on board space and 25% on cost as opposed to a discrete implementation. Since the IC is designed on a process geared toward analog and mixed-signal capabilities, there are no compromises on the audio performance or the efficiency of the dc/dc converters.

Fig. 2. This level of partitioning could result in savings of 50% on board space and 25% on cost as opposed to a discrete implementation.

This approach also allows for a faster time to market as time is not spent on selecting individual components and much of the power management complexity is handled in the IC with battery management, startup power supply sequencing and sleep mode implementation. This partitioned solution lends itself not only to the production of multiple product variants, but also to evolution as market needs change. ■

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