DDR3 tester has advanced timing debug

The Kibra 380 standalone protocol analyzer for DDR3 has improved software with new debug features for finding and resolving memory integration issues for comprehensive DDR3 bus and JEDEC timing analysis. The system now supports LR-DIMM testing and includes productivity features like overlay mode and CrossSync synchronization.

The analyzer uses dedicated triggering logic to identify over 65 unique JEDEC command and timing violations in real-time. A software-based state listing and waveform viewer allows precise timing measurements between command, address, and control signals. Detailed event statistics are reported by bank and rank to provide insights into overall memory utilization. In overlay mode, all signal lines can be floated for easy visual comparison. The CrossSync framework allows other analyzer platforms to be synchronized to provide time-aligned display of protocol traffic across different busses. ($58,000 — available now.)

By Richard Comerford

LeCroy , Chestnut Ridge , NY
Customer Care Center 800-453-2769
http://www.lecroy.com