Design Challenges for an Ultra-Low-Jitter Clock Synthesizer

Design Challenges for an Ultra-Low-Jitter Clock Synthesizer

This application note presents a design idea for an ultra-low-jitter clock synthesizer. The target performance is  

This is a reference design for a low-jitter clock source for high-speed data converters. The goal is to achieve

Design Requirements:

The maximum intended frequency for this clock design is 2GHz. However, there are alternate VCOs (voltage-controlled oscillators) and prescalers available that can extend the frequency higher, each device producing differing results. This reference design, simulation tests, and results are focused on performance only at 2GHz output frequency.

Some high-speed converters use both edges of the clock signal for internal timing. Consequently, a critical design requirement is a 50% duty cycle. Additionally, the targeted output drive is 10dBm into 50Ω, or a 2VP-P differential.

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