The Vista comprehensive architecture design and prototyping platform now allows users to model, analyze, and optimize power at the transaction level of abstraction. The tool provides a “layered” behavioral, timing, and power-modeling design methodology coupled with the SystemC Transaction-level Modeling Standard (TLM-2.0) supported by the Open SystemC Initiative (OSCI).
In addition, it allows chip designers and system architects to make viable decisions on hardware/software partitioning and architecture structures. With its advanced debug and analysis toolset, users can verify system-wide functionality, analyze and optimize systems under realistic traffic loads, and adjust system resources for optimal performance and power. Users can also explore various voltage-scaling and shutdown techniques and apply the most efficient power management strategies. (From $100,000 — available now.)
Mentor Graphics , Wilsonville , OR
Sales 503-685-7000
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