DS098

0 QPro Virtex-E 1.8V QML R High-Reliability FPGAs DS098-1 (v1.1) July 29, 2004 Advance Product Specification 0 0 Features – 200 Mb/s DDR SDRAMs · Cer tified to MIL-PRF-38535 (Qualified Manufacturer Listing) – Suppor ted by free Synthesizable reference design · Guaranteed over the full military temperature range · High-Performance Built-In Clock Management Circuitry (­55°C to +125°C) – Eight fully digital Delay-Locked Loops (DLLs) · Ceramic and Plastic Packages – Digitally-Synthesized 50% duty cycle for Double · Fast, High-Density 1.8V FPGA Family Data Rate (DDR) Applications – Densities from 600K to 2M system gates – Clock Multiply and Divide – 130 MHz internal performance (four LUT levels) – Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard – Designed for low-power operation · Flexible Architecture Balances Speed and Density – PCI compliant 3.3V, 32-bit, 33 MHz – Dedicated carry logic for high-speed arithmetic · Highly Flexible SelectIOTM+ Technology – Dedicated multiplier support – Suppor ts 20 high-performance interface standards – Cascade chain for wide-input function – Up to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth of > 100 Gb/s – Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset · Differential Signalling Support – Internal 3-state bussing – LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL – IEEE 1149.1 boundary-scan logic – Differential I/O signals can be input, output, or I/O – Die-temperature sensor diode – Compatible with standard differential devices · Suppor ted by Xilinx FoundationTM and Alliance SeriesTM – LVPECL and LVDS clock inputs for 300+ MHz Development Systems clocks – Fur ther compile time reduction of 50% · Proprietar y High-Performance SelectLink Technology – Internet Team Design (ITD) tool ideal for – Double Data Rate (DDR) to VirtexTM-E link million-plus gate density designs – Web-based HDL generation methodology – Wide selection of PC and workstation platforms · Sophisticated SelectRAM+TM Memory Hierarchy · SRAM-Based In-System Configuration – 600 Kb of internal configurable distributed RAM – Unlimited reprogrammability – Up to 640 Kb of synchronous internal block RAM · Advanced Packaging Options – Dual port block RAM capability – 1.0 mm BGA – Memory bandwidth up to 1.66 Tb/s (equivalent – 1.27 mm BGA bandwidth of over 100 RAMBUS channels) 0.18 µm 6-Layer Metal Process · – Designed for high-performance Interfaces to External Memories · 100% Factory Tested – 200 MHz ZBT* SRAMs · 100% Factory Tested * ZBT is a trademark of Integrated Device Technology, Inc.

© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS098-1 (v1.1) July 29, 2004 www.xilinx.com Module 1 of 4 Advance Product Specification 1-800-255-7778 1 Features · Certified to MIL-PRF-38535 (Qualified Manufacturer Listing) · Guaranteed over the full military temperature range (­55°C to +125°C) · Ceramic and Plastic Packages · Fast, High-Density 1.8V FPGA Family – Densities from 600K to 2M system gates – 130 MHz internal performance (four LUT levels) – Designed for low-power operation – PCI compliant 3.3V, 32-bit, 33 MHz · Highly Flexible SelectIOTM+ Technology – Supports 20 high-performance interface standards – Up to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth of > 100 Gb/s · Differential Signalling Support – LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL – Differential I/O signals can be input, output, or I/O – Compatible with standard differential devices – LVPECL and LVDS clock inputs for 300+ MHz clocks · Proprietary High-Performance SelectLink Technology – Double Data Rate (DDR) to VirtexTM-E link – Web-based HDL generation methodology · Sophisticated SelectRAM+TM Memory Hierarchy – 600 Kb of internal configurable distributed RAM – Up to 640 Kb of synchronous internal block RAM – Dual port block RAM capability – Memory bandwidth up to 1.66 Tb/s (equivalent bandwidth of over 100 RAMBUS channels) – Designed for high-performance Interfaces to External Memories – 200 MHz ZBT* SRAMs – 200 Mb/s DDR SDRAMs – Supported by free Synthesizable reference design · High-Performance Built-In Clock Management Circuitry – Eight fully digital Delay-Locked Loops (DLLs) – Digitally-Synthesized 50% duty cycle for Double Data Rate (DDR) Applications – Clock Multiply and Divide – Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard · Flexible Architecture Balances Speed and Density – Dedicated carry logic for high-speed arithmetic – Dedicated multiplier support – Cascade chain for wide-input function – Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset – Internal 3-state bussing – IEEE 1149.1 boundary-scan logic – Die-temperature sensor diode · Supported by Xilinx FoundationTM and Alliance SeriesTM Development Systems – Further compile time reduction of 50% – Internet Team Design (ITD) tool ideal for million-plus gate density designs – Wide selection of PC and workstation platforms · SRAM-Based In-System Configuration – Unlimited reprogrammability · Advanced Packaging Options – 1.0 mm BGA – 1.27 mm BGA · 0.18 µm 6-Layer Metal Process · 100% Factory Tested · 100% Factory Tested * ZBT is a trademark of Integrated Device Technology, Inc. 0 QPro Virtex-E 1.8V QML High-Reliability FPGAs DS098-1 (v1.1) July 29, 2004 0 0 Advance Product Specification R Table 1: Virtex-E Field-Programmable Gate Array Family Members Device System Gates Logic Gates CLB Array Logic Cells Differential I/O Pairs User I/O Block RAM Bits Distributed RAM Bits XQV600E 985,882 186,624 48 x 72 15,552 247 316 294,912 221,184 XQV1000E 1,569,178 331,776 64 x 96 27,648 281 404 393,216 393,216 XQV2000E 2,541,952 518,400 80 x 120 43,200 344 804 655,360 614,400 QPro Virtex-E 1.8V QML High-Reliability FPGAs R Module 1 of 4 www.xilinx.com DS098-1 (v1.1) July 29, 2004 2 1-800-255-7778 Advance Product Specification Virtex-E Compared to Virtex Devices The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchro- nous system performance up to 240 MHz using sin- gled-ended SelectIO technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins per signal. Almost all signal pins can be used for these new standards. Virtex-E devices have up to 640 Kb of faster (250 MHz) block SelectRAM, but the individual RAMs are the same size and structure as in the Virtex family. They also have eight DLLs instead of the four in Virtex devices. Each indi- vidual DLL is slightly improved with easier clock mirroring and 4x frequency multiplication. VCCINT, the supply voltage for the internal logic and mem- ory, is 1.8V, instead of 2.5V for Virtex devices. Advanced processing and 0.18 µm design rules have resulted in smaller dice, faster speed, and lower power consumption. I/O pins are 3V tolerant, and can be 5V tolerant with an external 100 resistor. PCI 5V is not supported. With the addition of appropriate external resistors, any pin can toler- ate any voltage desired. Banking rules are different. With Virtex devices, all input buffers are powered by VCCINT. With Virtex-E devices, the LVTTL, LVCMOS2, and PCI input buffers are powered by the I/O supply voltage VCCO. The Virtex-E family is not bitstream-compatible with the Vir- tex family, but Virtex designs can be compiled into equiva- lent Virtex-E devices. The same device in the same package for the Virtex-E and Virtex families are pin-compatible with some minor excep- tions. See the data sheet pinout section for details. General Description The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 µm CMOS process. These advances make Virtex-E FPGAs powerful and flexible alter- natives to mask-programmed gate arrays. The QPro Vir- tex-E family includes the three members in Table 1. Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in program- mable logic design. Combining a wide variety of program- mable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. Virtex-E Architecture Virtex-E devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) sur- rounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Con- figuration data can be read from an external SPROM (mas- ter serial mode), or can be written into the FPGA (SelectMAPTM, slave serial, and JTAG modes). The standard Xilinx Foundation Series and Alliance Series Development systems deliver complete design support for Virtex-E, covering every aspect from behavioral and sche- matic entry, through simulation, automatic design transla- tion and implementation, to the creation and downloading of a configuration bit stream. Higher Performance Virtex-E devices provide better performance than previous generations of FPGAs. Designs can achieve synchronous system clock rates up to 240 MHz including I/O or 622 Mb/s using Source Synchronous data transmission architech- tures. Virtex-E I/Os comply fully with 3.3V PCI specifica- tions, and interfaces can be implemented that operate at 33 MHz or 66 MHz. While performance is design-dependent, many designs operate internally at speeds in excess of 133 MHz and can achieve over 311 MHz. QPro Virtex-E 1.8V QML High-Reliability FPGAs R DS098-1 (v1.1) July 29, 2004 www.xilinx.com Module 1 of 4 Advance Product Specification 1-800-255-7778 3 Virtex-E Device/Package Combinations and Maximum I/O Virtex-E Ordering Information Table 2: Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) XQV600E XQV1000E XQV2000E BG432 316 – – BG560 – 404 404 CG560 – 404 – FG1156 – – 804 XQV600E -6 BG 432 MExample: Temperature Range/Grade Number of Pins Package Type Device Type Speed Grade(1) Device Ordering Options Device Type Package Grade Temperature XQV600E BG432 432-ball Plastic BGA Package M Military Ceramic TC = ­55°C to +125°C XQV1000E BG560 560-ball Plastic BGA Package N Military Plastic TJ = ­55°C to +125°C XQV2000E FG1156 1156-ball Plastic Fine Pitch BGA Package CG560 560-column Ceramic Column Grid Package Notes: 1. -6 only supported speed grade. Valid Ordering Combinations M Grade N Grade XQV1000E-6CG560M XQV600E-6BG432N XQV1000E-6BG560N XQV2000E-6BG560N XQV2000E-6FG1156N QPro Virtex-E 1.8V QML High-Reliability FPGAs R Module 1 of 4 www.xilinx.com DS098-1 (v1.1) July 29, 2004 4 1-800-255-7778 Advance Product Specification Revision History The following table shows the revision history for this document. Date Version Revision 05/19/03 1.0 Initial Xilinx release. 07/29/04 1.1 · Device/Package Availability and Ordering Information tables on page 3: Removed references to devices in CB228 and HQ240 packages (not offered). · Device Ordering Options table on page 3: Removed Footnote (2) referring to Class Q order codes (not offered). · Table 1: Corrected number of available User I/Os to conform to numbers in Table 2. © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS098-2 (v1.1) July 29, 2004 www.xilinx.com Module 2 of 4 Advance Product Specification 1-800-255-7778 1 Architectural Description Virtex-E Array The VirtexTM-E user-programmable gate array, shown in Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks (IOBs). · CLBs provide the functional elements for constructing logic · IOBs provide the interface between the package pins and the CLBs CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. Each CLB nests into a VersaBlock that also provides local routing resources to connect the CLB to the GRM. The VersaRingTM I/O interface provides additional routing resources around the periphery of the device. This routing improves I/O routability and facilitates pin locking. The Virtex-E architecture also includes the following circuits that connect to the GRM. · Dedicated block memories of 4096 bits each · Clock DLLs for clock-distribution delay compensation and clock domain control · 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resources Values stored in static memory cells control the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device. Input/Output Block The Virtex-E IOB, Figure 2, features SelectIOTM+ inputs and outputs that support a wide variety of I/O signalling stan- dards, see Table 1. The three IOB storage elements function either as edge- triggered D-type flip-flops or as level-sensitive latches. Each IOB has a clock signal (CLK) shared by the three flip-flops and independent clock enable signals for each flip-flop. In addition to the CLK and CE control signals, the three flip- flops share a Set/Reset (SR). For each flip-flop, this signal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asyn- chronous Clear. The output buffer and all of the IOB control signals have independent polarity controls. All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. After configuration, clamping diodes are connected to VCCO with the exception of LVCMOS18, LVCMOS25, GTL, GTL+, LVDS, and LVPECL. 0 QPro Virtex-E 1.8V QML High- Reliability FPGAs DS098-2 (v1.1) July 29, 2004 0 0 Advance Product Specification R Figure 1: Virtex-E Architecture Overview DLLDLL IOBs IOBs VersaRing VersaRing ds022_01_121099 CLBs BRAMs BRAMs BRAMs CLBs CLBs BRAMs CLBs DLLDLL DLLDLLDLLDLL Figure 2: Virtex-E Input/Output Block (IOB) OBUFT IBUF Vref ds022_02_091300 SR CLK ICE OCE O I IQ T TCE D CE Q SR D CE Q SR D CE Q SR PAD Programmable Delay Weak Keeper QPro Virtex-E 1.8V QML High-Reliability FPGAs R Module 2 of 4 www.xilinx.com DS098-2 (v1.1) July 29, 2004 2 1-800-255-7778 Advance Product Specification Optional pull-up, pull-down and weak-keeper circuits are attached to each pad. Prior to configuration all outputs not involved in configuration are forced into their high-imped- ance state. The pull-down resistors and the weak-keeper circuits are inactive, but I/Os can optionally be pulled up. The activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. If the pull-up resistors are not activated, all the pins are in a high-impedance state. Consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. All Virtex-E IOBs support IEEE 1149.1-compatible bound- ary scan testing. Input Path The Virtex-E IOB input path routes the input signal directly to internal logic and/ or through an optional input flip-flop. An optional delay element at the D-input of this flip-flop elim- inates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signalling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in close prox- imity to each other. See “I/O Banking” on page 2. There are optional pull-up and pull-down resistors at each user I/O input for use after configuration. Their value is in the range 50-100 k. Output Path The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flip-flop. The 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides syn- chronous enable and disable. Each output driver can be individually programmed for a wide range of low-voltage signalling standards. Each output buffer can source up to 24 mA and sink up to 48 mA. Drive strength and slew rate controls minimize bus transients. In most signalling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other. See “I/O Bank- ing” on page 2. An optional weak-keeper circuit is connected to each out- put. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal. If the pin is connected to a multiple-source sig- nal, the weak keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. Since the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate VREF voltage must be provided if the signalling standard requires one. The provi- sion of this voltage must comply with the I/O banking rules. I/O Banking Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are externally sup- plied and connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure 3. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use. Table 1: Supported I/O Standards I/O Standard Output VCCO Input VCCO Input VREF Board Termination Voltage (VTT) LVTTL 3.3 3.3 N/A N/A LVCMOS2 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A SSTL3 I & II 3.3 N/A 1.50 1.50 SSTL2 I & II 2.5 N/A 1.25 1.25 GTL N/A N/A 0.80 1.20 GTL+ N/A N/A 1.0 1.50 HSTL I 1.5 N/A 0.75 0.75 HSTL III & IV 1.5 N/A 0.90 1.50 CTT 3.3 N/A 1.50 1.50 AGP-2X 3.3 N/A 1.32 N/A PCI33_3 3.3 3.3 N/A N/A PCI66_3 3.3 3.3 N/A N/A BLVDS & LVDS 2.5 N/A N/A N/A LVPECL 3.3 N/A N/A N/A QPro Virtex-E 1.8V QML High-Reliability FPGAs R DS098-2 (v1.1) July 29, 2004 www.xilinx.com Module 2 of 4 Advance Product Specification 1-800-255-7778 3 Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 2. GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are auto- matically configured as inputs for the VREF voltage. Approx- imately one in six of the I/O pins in the bank assume this role. The VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be con- nected to the external voltage source for correct operation. Within a bank, inputs that require VREF can be mixed with those that do not. However, only one VREF voltage can be used within a bank. In Virtex-E, input buffers with LVTTL, LVCMOS2, LVCMOS18, PCI33_3, PCI66_3 standards are supplied by VCCO rather than VCCINT. For these standards, only input and output buffers that have the same VCCO can be mixed together. The VCCO and VREF pins for each bank appear in the device pin-out tables and diagrams. The diagrams also show the bank affiliation of each I/O. Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a super set of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All the VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O. In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or can be connected to the VCCO voltage to permit migration to a larger device if necessary. Configurable Logic Blocks The basic building block of the Virtex-E CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop. Each Virtex-E CLB contains four LCs, organized in two similar slices, as shown in Figure 4. Figure 5 shows a more detailed view of a single slice. In addition to the four basic LCs, the Virtex-E CLB contains logic that combines function generators to provide functions of five or six inputs. Consequently, when estimating the number of system gates provided by a given device, each CLB counts as 4.5 LCs. Look-Up Tables Virtex-E function generators are implemented as 4-input look-up tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the two LUTs within a slice can be com- bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16 x 1-bit dual-port synchronous RAM. The Virtex-E LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as Digital Signal Processing. Figure 3: Virtex-E I/O Banks Table 2: Compatible Output Standards VCCO Compatible Standards 3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, GTL+, LVPECL 2.5V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+, BLVDS, LVDS 1.8V LVCMOS18, GTL, GTL+ 1.5V HSTL I, HSTL III, HSTL IV, GTL, GTL+ ds022_03_121799 Bank 0 GCLK3 GCLK2 GCLK1 GCLK0 Bank 1 Bank 5 Bank 4 VirtexE Device Bank7Bank6 Bank2Bank3 QPro Virtex-E 1.8V QML High-Reliability FPGAs R Module 2 of 4 www.xilinx.com DS098-2 (v1.1) July 29, 2004 4 1-800-255-7778 Advance Product Specification Storage Elements The storage elements in the Virtex-E slice can be config- ured either as edge-triggered D-type flip-flops or as level- sensitive latches. The D inputs can be driven either by the function generators within the slice or directly from slice inputs, bypassing the function generators. In addition to Clock and Clock Enable signals, each Slice has synchronous set and reset signals (SR and BY). SR Figure 4: 2-Slice Virtex-E CLB F1 F2 F3 F4 G1 G2 G3 G4 Carry & Control Carry & Control Carry & Control Carry & Control LUT CINCIN COUT COUT YQ XQXQ YQ X XB Y YBYB Y BX BY BX BY G1 G2 G3 G4 F1 F2 F3 F4 Slice 1 Slice 0 XB X LUTLUT LUT D CE Q RC SP D CE Q RC SP D CE Q RC SP D CE Q RC SP ds022_04_121799 Figure 5: Detailed View of Virtex-E Slice BY F5IN SR CLK CE BX YB Y YQ XB X XQ G4 G3 G2 G1 F4 F3 F2 F1 CIN 0 1 1 0 F5 F5 ds022_05_092000 COUT CY D CE Q D CE Q F6 CK WSO WSH WE A4 BY DG BX DI DI O WEI3 I2 I1 I0 LUT CY I3 I2 I1 I0 O DIWE LUT INIT INIT REV REV QPro Virtex-E 1.8V QML High-Reliability FPGAs R DS098-2 (v1.1) July 29, 2004 www.xilinx.com Module 2 of 4 Advance Product Specification 1-800-255-7778 5 forces a storage element into the initialization state speci- fied for it in the configuration. BY forces it into the opposite state. Alternatively, these signals can be configured to oper- ate asynchronously. All of the control signals are indepen- dently invertible, and are shared by the two flip-flops within the slice. Additional Logic The F5 multiplexer in each slice combines the function gen- erator outputs. This combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the F5- multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected functions of up to 19 inputs. Each CLB has four direct feedthrough paths, two per slice. These paths provide extra data input lines or additional local routing that does not consume logic resources. Arithmetic Logic Dedicated carry logic provides fast arithmetic carry capabil- ity for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB. The arithmetic logic includes an XOR gate that allows a 2- bit full adder to be implemented within a slice. In addition, a dedicated AND gate improves the efficiency of multiplier implementation. The dedicated carry path can also be used to cascade function generators for implementing wide logic functions. BUFTs Each Virtex-E CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses. See “Dedicated Routing” on page 6. Each Virtex-E BUFT has an independent 3-state control pin and an independent input pin. Block SelectRAM Virtex-E FPGAs incorporate large block SelectRAM memo- ries. These complement the Distributed SelectRAM memo- ries that provide shallow RAM structures implemented in CLBs. Block SelectRAM memory blocks are organized in columns, starting at the left (column 0) and right outside edges and inserted every 12 CLB columns (see notes for smaller devices). Each memory block is four CLBs high, and each memory column extends the full height of the chip, immedi- ately adjacent (to the right, except for column 0) of the CLB column locations indicated in Table 3. Table 4 shows the amount of block SelectRAM memory that is available in each Virtex-E device. As illustrated in Figure 6, each block SelectRAM cell is a fully synchronous dual-ported (True Dual Port) 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured indepen- dently, providing built-in bus-width conversion. Table 5 shows the depth and width aspect ratios for the block SelectRAM. The Virtex-E block SelectRAM also includes dedicated routing to provide an efficient interface with both CLBs and other block SelectRAMs. Refer to XAPP130 for block SelectRAM timing waveforms. Table 3: CLB/Block RAM Column Locations XQ Device Column Number 0 12 24 36 48 60 72 84 96 108 120 V600E V1000E V2000E Table 4: Virtex-E Block SelectRAM Amounts Virtex-E Device # of Blocks Block SelectRAM Bits XQV600E 72 294,912 XQV1000E 96 393,216 XQV2000E 160 655,360 Figure 6: Dual-Port Block SelectRAM Table 5: Block SelectRAM Port Aspect Ratios Width Depth ADDR Bus Data Bus 1 4096 ADDR<_113a_0> DATA 2 2048 ADDR<_103a_0> DATA<_13a_0> WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] DOA[#:0] DOB[#:0] RAMB4_S#_S# ds022_06_121699 QPro Virtex-E 1.8V QML High-Reliability FPGAs R Module 2 of 4 www.xilinx.com DS098-2 (v1.1) July 29, 2004 6 1-800-255-7778 Advance Product Specification Programmable Routing Matrix It is the longest delay path that limits the speed of any worst- case design. Consequently, the Virtex-E routing architec- ture and its place-and-route software were defined in a joint optimization process. This joint optimization minimizes long-path delays, and consequently, yields the best system performance. The joint optimization also reduces design compilation times because the architecture is software-friendly. Design cycles are correspondingly reduced due to shorter design iteration times. Local Routing The VersaBlock provides local routing resources (see Figure 7), providing three types of connections: · Interconnections among the LUTs, flip-flops, and GRM · Internal CLB feedback paths that provide high-speed connections to LUTs within the same CLB, chaining them together with minimal routing delay · Direct paths that provide high-speed connections between horizontally adjacent CLBs, eliminating the delay of the GRM. General Purpose Routing Most Virtex-E signals are routed on the general purpose routing, and consequently, the majority of interconnect resources are associated with this level of the routing hier- archy. General-purpose routing resources are located in horizontal and vertical routing channels associated with the CLB rows and columns and are as follows: · Adjacent to each CLB is a General Routing Matrix (GRM). The GRM is the switch matrix through which horizontal and vertical routing resources connect, and is also the means by which the CLB gains access to the general purpose routing. · 24 single-length lines route GRM signals to adjacent GRMs in each of the four directions. · 72 buffered Hex lines route GRM signals to another GRMs six-blocks away in each one of the four directions. Organized in a staggered pattern, Hex lines are driven only at their endpoints. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). One third of the Hex lines are bidirectional, while the remaining ones are uni-directional. · 12 Longlines are buffered, bidirectional wires that distribute signals across the device quickly and efficiently. Vertical Longlines span the full height of the device, and horizontal ones span the full width of the device. I/O Routing Virtex-E devices have additional routing resources around their periphery that form an interface between the CLB array and the IOBs. This additional routing, called the VersaRing, facilitates pin-swapping and pin-locking, such that logic redesigns can adapt to existing PCB layouts. Time-to-market is reduced, since PCBs and other system components can be manufactured while the logic design is still in progress. Dedicated Routing Some classes of signal require dedicated routing resources to maximize performance. In the Virtex-E architecture, dedi- cated routing resources are provided for two classes of signal. · Horizontal routing resources are provided for on-chip 3- state busses. Four partitionable bus lines are provided per CLB row, permitting multiple busses within a row, as shown in Figure 8. · Two dedicated nets per CLB propagate carry signals vertically to the adjacent CLB.Global Clock Distribution Network · DLL Location 4 1024 ADDR<_93a_0> DATA<_33a_0> 8 512 ADDR<_83a_0> DATA<_73a_0> 16 256 ADDR<_73a_0> DATA<_153a_0> Figure 7: Virtex-E Local Routing Table 5: Block SelectRAM Port Aspect Ratios Width Depth ADDR Bus Data Bus XCVE_ds_007 CLB GRM To Adjacent GRM To Adjacent GRM Direct Connection To Adjacent CLB To Adjacent GRM To Adjacent GRM Direct Connection To Adjacent CLB 0>