May 5, 1993 RM IDT SARAM
Dual-port SRAM has serial/parallel access
One port looks like a clocked two-way FIFO, the other like a normal SRAM
The IDT70825 memory looks something like a video RAM, with static rather
than dynamic storage. The 8-K x 16-bit sequential-access/random-access
memory (SARAM) is aimed at buffering for flow control in internetwork
bridges, disk arrays, and telecom (see diagram). The sequential-access
side of the 70825 has the same controls as a bidirectional synchronous
FIFO memory with cycle times of 30, 40, or 50 ns, corresponding to
random-access grades of 25, 35, and 45 ns. Six-transistor cells allow true
dual-port access with two exceptions. First, simultaneous writes to the
same cell are not allowed. Second, a cell cannot be read from one port
while the other port is writing to it. Otherwise, unsynchronized accesses
via both ports do not interfere with each other. The behavior of the
sequential access is controlled by six registers, all 16 bits long,
allowing for family expansion. Register access is determined by a command
CMD pin, mutually exclusive with the chip enable. The array can be
divided into two buffers of arbitrary size. The buffers can be chained or
wrapped around, and the two can be configured for different modes. The
whole array can be configured as a single circular buffer. The parts can
be cascaded for 32-bit bus width. (IDT70825 in an 80-pin, thin quad
flatpack, from $49.35 ea/1,000–samples now.) Integrated Device
Technology, Inc. Santa Clara, CA Carl May 408-754-4623 Fax 408-492-8674
CAPTION:
Simultaneous access from sequential and random ports to the same array
makes the SARAM a natural for disk buffering. Out-of-order sectors in the
sequential-write stream can be read from the random port in the correct
order.
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