EDA tool interfaces to Cadence Allegro PCB SI

EDA tool interfaces to Cadence Allegro PCB SI

The TimingDesigner 9.2 EDA tool interfaces with the Cadence Allegro PCB Signal Integrity (SI) technology — providing users with a complete SI and timing design environment. Engineers can now combine the accuracy of simulation with an interactive, comprehensive timing diagram solution to quickly determine if today’s shrinking timing margins are in spec.

The TimingDesigner graphical interface makes developing and performing analysis on complex timing relationships easy, while enabling review of the entire signal path. For ASIC and FPGA design customers, this new version includes enhanced support for SDC generation, 65-nm-and-below support for Altera FPGAs, and a new interface to the Actel Libero development environment. (From $2,640 for 1-year license — late August.)

EMA Design Automation , Rochester , NY
Information 585-334-6001

http://www.ema-eda.com