EDA tool targets nanometer designs

Targeting transistor-level statistical design and verification for nanometer designs, the SolidoSTAT EDA tool allows chip designers to gain insight into the effects of process variations on their design. The suite includes five tools: the SolidoSTAT Sampler, Characterizer, Circuit Enhancer, Tradeoff Analyzer, and Visualizer.

The Sampler accelerates traditional Monte Carlo analysis through parallel processing and high-efficiency sampling algorithms, while the Circuit Enhancer automatically and intelligently explores sizing alternatives to improve the circuit’s robustness. The Tradeoff Analyzer mines Sampler results, without additional simulations, to identify tradeoffs between specifications that improve yield. Also, the Visualizer converts raw data from the Analyzer into dynamic visual representations and the Characterizer uses algorithms to pinpoint sources of yield and performance loss in the design, (Call company for pricing and availability.)

Solido Design Automation , Saskatoon , Canada
Information 306-382-4100
http://www.solidodesign.com