Floorplanner speeds
submicron ASIC design
ChipPlanner is a floorplanning tool in the company's Navigator Series of
ASIC and IC design tools. The vendor-independent tool provides
comprehensive floorplanning, placement, and timing analysis features
including a tight link between synthesis and layout tools for incremental
placement and timing optimization. ChipPlanner uses actual placement of
gates along critical paths to improve the accuracy of interconnect timing
calculations and reduce place-and-route iterations for submicron ASICs.
Initial support for the tool includes gate array libraries from Hitachi,
Raytheon, ES2/US2, and VLSI Technology. ChipPlanner runs on workstations
from Digital Equipment, Hewlett-Packard, IBM, and Sun Microsystems.
(From $30,000–available now.)
COMPASS Design Automation, Inc.
San Jose, CA Steve Kompolt
408-434-7687
Fax 408-434-7820
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