Formal verification tool runs early in process

Formal verification tool runs early in process

Ascent software for automatic formal verification of electronic designs finds bugs in Register-transfer-level (RTL) designs and improves design quality. It is said to provide more precise analysis than syntactic checkers or lint tools, since formal analysis takes actual circuit functionality into account.

The tool’s latest version yields a significant speed improvement, and its redesigned architecture is focused on automatic checks that are derived directly from the RTL design. The verification is applied early in the design cycle, even before the blocks are assembled into subunits and before simulation test benches are developed. (From $35,000, one year licenseavailable now.)

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